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  • 13 commits
  • 17 files changed
  • 1 contributor

Commits on Nov 1, 2016

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Commits on Nov 2, 2016

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  3. Changelog for Yosys 0.7

    cliffordwolf committed Nov 2, 2016
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Commits on Nov 3, 2016

  1. Yosys 0.7

    cliffordwolf committed Nov 3, 2016
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99 changes: 99 additions & 0 deletions CHANGELOG
Original file line number Diff line number Diff line change
@@ -3,6 +3,105 @@ List of major changes and improvements between releases
=======================================================


Yosys 0.6 .. Yosys 0.7
----------------------

* Various
- Added "yosys -D" feature
- Added support for installed plugins in $(DATDIR)/plugins/
- Renamed opt_const to opt_expr
- Renamed opt_share to opt_merge
- Added "prep -flatten" and "synth -flatten"
- Added "prep -auto-top" and "synth -auto-top"
- Using "mfs" and "lutpack" in ABC lut mapping
- Support for abstract modules in chparam
- Cleanup abstract modules at end of "hierarchy -top"
- Added tristate buffer support to iopadmap
- Added opt_expr support for div/mod by power-of-two
- Added "select -assert-min <N> -assert-max <N>"
- Added "attrmvcp" pass
- Added "attrmap" command
- Added "tee +INT -INT"
- Added "zinit" pass
- Added "setparam -type"
- Added "shregmap" pass
- Added "setundef -init"
- Added "nlutmap -assert"
- Added $sop cell type and "abc -sop -I <num> -P <num>"
- Added "dc2" to default ABC scripts
- Added "deminout"
- Added "insbuf" command
- Added "prep -nomem"
- Added "opt_rmdff -keepdc"
- Added "prep -nokeepdc"
- Added initial version of "synth_gowin"
- Added "fsm_expand -full"
- Added support for fsm_encoding="user"
- Many improvements in GreenPAK4 support
- Added black box modules for all Xilinx 7-series lib cells
- Added synth_ice40 support for latches via logic loops
- Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"

* Build System
- Added ABCEXTERNAL and ABCURL make variables
- Added BINDIR, LIBDIR, and DATDIR make variables
- Added PKG_CONFIG make variable
- Added SEED make variable (for "make test")
- Added YOSYS_VER_STR make variable
- Updated min GCC requirement to GCC 4.8
- Updated required Bison version to Bison 3.x

* Internal APIs
- Added ast.h to exported headers
- Added ScriptPass helper class for script-like passes
- Added CellEdgesDatabase API

* Front-ends and Back-ends
- Added filename glob support to all front-ends
- Added avail (black-box) module params to ilang format
- Added $display %m support
- Added support for $stop Verilog system task
- Added support for SystemVerilog packages
- Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
- Added support for "active high" and "active low" latches in read_blif and write_blif
- Use init value "2" for all uninitialized FFs in BLIF back-end
- Added "read_blif -sop"
- Added "write_blif -noalias"
- Added various write_blif options for VTR support
- write_json: also write module attributes.
- Added "write_verilog -nodec -nostr -defparam"
- Added "read_verilog -norestrict -assume-asserts"
- Added support for bus interfaces to "read_liberty -lib"
- Added liberty parser support for types within cell decls
- Added "write_verilog -renameprefix -v"
- Added "write_edif -nogndvcc"

* Formal Verification
- Support for hierarchical designs in smt2 back-end
- Yosys-smtbmc: Support for hierarchical VCD dumping
- Added $initstate cell type and vlog function
- Added $anyconst and $anyseq cell types and vlog functions
- Added printing of code loc of failed asserts to yosys-smtbmc
- Added memory_memx pass, "memory -memx", and "prep -memx"
- Added "proc_mux -ifx"
- Added "yosys-smtbmc -g"
- Deprecated "write_smt2 -regs" (by default on now)
- Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
- Added support for memories to smtio.py
- Added "yosys-smtbmc --dump-vlogtb"
- Added "yosys-smtbmc --smtc --dump-smtc"
- Added "yosys-smtbmc --dump-all"
- Added assertpmux command
- Added "yosys-smtbmc --unroll"
- Added $past, $stable, $rose, $fell SVA functions
- Added "yosys-smtbmc --noinfo and --dummy"
- Added "yosys-smtbmc --noincr"
- Added "yosys-smtbmc --cex <filename>"
- Added $ff and $_FF_ cell types
- Added $global_clock verilog syntax support for creating $ff cells
- Added clk2fflogic


Yosys 0.5 .. Yosys 0.6
----------------------

2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
@@ -72,7 +72,7 @@ else
LDLIBS += -lrt
endif

YOSYS_VER := 0.6+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 5869d26da021.. | wc -l; })
YOSYS_VER := 0.7+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 61f6811.. | wc -l; })
GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o

92 changes: 84 additions & 8 deletions backends/verilog/verilog_backend.cc
Original file line number Diff line number Diff line change
@@ -33,10 +33,11 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

bool norename, noattr, attr2comment, noexpr, nodec, nostr, defparam;
bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam;
int auto_name_counter, auto_name_offset, auto_name_digits;
std::map<RTLIL::IdString, int> auto_name_map;
std::set<RTLIL::IdString> reg_wires, reg_ct;
std::string auto_prefix;

RTLIL::Module *active_module;

@@ -85,13 +86,14 @@ void reset_auto_counter(RTLIL::Module *module)
for (size_t i = 10; i < auto_name_offset + auto_name_map.size(); i = i*10)
auto_name_digits++;

for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it)
log(" renaming `%s' to `_%0*d_'.\n", it->first.c_str(), auto_name_digits, auto_name_offset + it->second);
if (verbose)
for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it)
log(" renaming `%s' to `%s_%0*d_'.\n", it->first.c_str(), auto_prefix.c_str(), auto_name_digits, auto_name_offset + it->second);
}

std::string next_auto_id()
{
return stringf("_%0*d_", auto_name_digits, auto_name_offset + auto_name_counter++);
return stringf("%s_%0*d_", auto_prefix.c_str(), auto_name_digits, auto_name_offset + auto_name_counter++);
}

std::string id(RTLIL::IdString internal_id, bool may_rename = true)
@@ -100,7 +102,7 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true)
bool do_escape = false;

if (may_rename && auto_name_map.count(internal_id) != 0)
return stringf("_%0*d_", auto_name_digits, auto_name_offset + auto_name_map[internal_id]);
return stringf("%s_%0*d_", auto_prefix.c_str(), auto_name_digits, auto_name_offset + auto_name_map[internal_id]);

if (*str == '\\')
str++;
@@ -157,14 +159,14 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
if (width < 0)
width = data.bits.size() - offset;
if (nostr)
goto dump_bits;
goto dump_hex;
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
if (width == 32 && !no_decimal && !nodec) {
int32_t val = 0;
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
goto dump_bits;
goto dump_hex;
if (data.bits[i] == RTLIL::S1)
val |= 1 << (i - offset);
}
@@ -173,7 +175,55 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
else
f << stringf("32'%sd%u", set_signed ? "s" : "", val);
} else {
dump_bits:
dump_hex:
if (nohex)
goto dump_bin;
vector<char> bin_digits, hex_digits;
for (int i = offset; i < offset+width; i++) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
case RTLIL::S0: bin_digits.push_back('0'); break;
case RTLIL::S1: bin_digits.push_back('1'); break;
case RTLIL::Sx: bin_digits.push_back('x'); break;
case RTLIL::Sz: bin_digits.push_back('z'); break;
case RTLIL::Sa: bin_digits.push_back('z'); break;
case RTLIL::Sm: log_error("Found marker state in final netlist.");
}
}
if (GetSize(bin_digits) == 0)
goto dump_bin;
while (GetSize(bin_digits) % 4 != 0)
if (bin_digits.back() == '1')
bin_digits.push_back('0');
else
bin_digits.push_back(bin_digits.back());
for (int i = 0; i < GetSize(bin_digits); i += 4)
{
char bit_3 = bin_digits[i+3];
char bit_2 = bin_digits[i+2];
char bit_1 = bin_digits[i+1];
char bit_0 = bin_digits[i+0];
if (bit_3 == 'x' || bit_2 == 'x' || bit_1 == 'x' || bit_0 == 'x') {
if (bit_3 != 'x' || bit_2 != 'x' || bit_1 != 'x' || bit_0 != 'x')
goto dump_bin;
hex_digits.push_back('x');
continue;
}
if (bit_3 == 'z' || bit_2 == 'z' || bit_1 == 'z' || bit_0 == 'z') {
if (bit_3 != 'z' || bit_2 != 'z' || bit_1 != 'z' || bit_0 != 'z')
goto dump_bin;
hex_digits.push_back('z');
continue;
}
int val = 8*(bit_3 - '0') + 4*(bit_2 - '0') + 2*(bit_1 - '0') + (bit_0 - '0');
hex_digits.push_back(val < 10 ? '0' + val : 'a' + val - 10);
}
f << stringf("%d'%sh", width, set_signed ? "s" : "");
for (int i = GetSize(hex_digits)-1; i >= 0; i--)
f << hex_digits[i];
}
if (0) {
dump_bin:
f << stringf("%d'%sb", width, set_signed ? "s" : "");
if (width == 0)
f << stringf("0");
@@ -1342,6 +1392,9 @@ struct VerilogBackend : public Backend {
log(" instead of a backslash prefix) are changed to short names in the\n");
log(" format '_<number>_'.\n");
log("\n");
log(" -renameprefix <prefix>\n");
log(" insert this prefix in front of auto-generated instance names\n");
log("\n");
log(" -noattr\n");
log(" with this option no attributes are included in the output\n");
log("\n");
@@ -1357,6 +1410,11 @@ struct VerilogBackend : public Backend {
log(" not bit pattern. This option decativates this feature and instead\n");
log(" will write out all constants in binary.\n");
log("\n");
log(" -nohex\n");
log(" constant values that are compatible with hex output are usually\n");
log(" dumped as hex values. This option decativates this feature and\n");
log(" instead will write out all constants in binary.\n");
log("\n");
log(" -nostr\n");
log(" Parameters and attributes that are specified as strings in the\n");
log(" original input will be output as strings by this back-end. This\n");
@@ -1376,6 +1434,9 @@ struct VerilogBackend : public Backend {
log(" only write selected modules. modules must be selected entirely or\n");
log(" not at all.\n");
log("\n");
log(" -v\n");
log(" verbose output (print new names of all renamed wires and cells)\n");
log("\n");
log("Note that RTLIL processes can't always be mapped directly to Verilog\n");
log("always blocks. This frontend should only be used to export an RTLIL\n");
log("netlist, i.e. after the \"proc\" pass has been used to convert all\n");
@@ -1387,13 +1448,16 @@ struct VerilogBackend : public Backend {
{
log_header(design, "Executing Verilog backend.\n");

verbose = false;
norename = false;
noattr = false;
attr2comment = false;
noexpr = false;
nodec = false;
nohex = false;
nostr = false;
defparam = false;
auto_prefix = "";

bool blackboxes = false;
bool selected = false;
@@ -1431,6 +1495,10 @@ struct VerilogBackend : public Backend {
norename = true;
continue;
}
if (arg == "-renameprefix" && argidx+1 < args.size()) {
auto_prefix = args[++argidx];
continue;
}
if (arg == "-noattr") {
noattr = true;
continue;
@@ -1447,6 +1515,10 @@ struct VerilogBackend : public Backend {
nodec = true;
continue;
}
if (arg == "-nohex") {
nohex = true;
continue;
}
if (arg == "-nostr") {
nostr = true;
continue;
@@ -1463,6 +1535,10 @@ struct VerilogBackend : public Backend {
selected = true;
continue;
}
if (arg == "-v") {
verbose = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);
1 change: 1 addition & 0 deletions frontends/ast/genrtlil.cc
Original file line number Diff line number Diff line change
@@ -1271,6 +1271,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);

int mem_width, mem_size, addr_bits;
is_signed = id2ast->is_signed;
id2ast->meminfo(mem_width, mem_size, addr_bits);

RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
6 changes: 6 additions & 0 deletions frontends/ast/simplify.cc
Original file line number Diff line number Diff line change
@@ -1510,6 +1510,7 @@ skip_dynamic_range_lvalue_expansion:;
}

int mem_width, mem_size, addr_bits;
bool mem_signed = children[0]->id2ast->is_signed;
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);

int data_range_left = children[0]->id2ast->children[0]->range_left;
@@ -1529,6 +1530,7 @@ skip_dynamic_range_lvalue_expansion:;

AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_data->str = id_data;
wire_data->is_signed = mem_signed;
current_ast_mod->children.push_back(wire_data);
current_scope[wire_data->str] = wire_data;
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
@@ -2894,6 +2896,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";

int mem_width, mem_size, addr_bits;
bool mem_signed = children[0]->id2ast->is_signed;
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);

AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
@@ -2906,6 +2909,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_data->str = id_data;
wire_data->is_reg = true;
wire_data->is_signed = mem_signed;
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data);
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
@@ -2967,6 +2971,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";

int mem_width, mem_size, addr_bits;
bool mem_signed = id2ast->is_signed;
id2ast->meminfo(mem_width, mem_size, addr_bits);

AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
@@ -2980,6 +2985,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_data->str = id_data;
wire_data->is_reg = true;
wire_data->is_signed = mem_signed;
if (block)
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data);
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