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gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
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dleibrandt authored and sbourdeauducq committed Nov 20, 2016
1 parent 2015fe9 commit 4a62e09
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -230,16 +230,16 @@ def __init__(self, cpu_type="or1k", **kwargs):
if i % 4 == 3:
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=1024))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=1024))

for i in range(2):
phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16384))

phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
self.submodules += phy
@@ -279,7 +279,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ofifo_depth=16384,
ififo_depth=4))

self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

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