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Increase RTIO FIFO depths in class NIST_CLOCK #623
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What is that sideband cooling pulse sequence that causes trouble? |
@dleibrandt your patch fails timing. |
...on master, but passes on release-2. |
So this will stay in release-2 and be available with 2.1 unless we have problems with it again, and will not be in 3.x. |
@sbourdeauducq any idea why the timing fails? |
@sbourdeauducq, the sideband cooling pulse sequence is up to 1000 pulses. The pulse durations change during the sequence, but the majority are roughly 1 us. Each pulse consists of turning a ttl on and off and setting a dds frequency and amplitude twice (once at the start and once at the end of the pulse; we do this so that we can keep the AOM on but detune the light from the atomic resonance, thus keeping the temperature of the AOM constant). I suspect that my underflow problem will be solved once DMA is finished. Will DMA be included in 3.x, or will it come later? |
DMA should be in 3.0. |
Support for AD9914 DDS phase modes in DMA sequences is currently unclear though. |
* master: (23 commits) RELEASE_NOTES: update pipistrello: add some inputs Remove last vestiges of nist_qc1. Fully drop AD9858 and kc705-nist_qc1 support (closes #576). coredevice.dds: reimplement fully in ARTIQ Python. compiler: unbreak casts to int32/int64. analyses.constness: fix false positive on x[...]. inferencer: significantly improve the op-assignment diagnostic. Fix tests. Move mu_to_seconds, seconds_to_mu to Core. artiq_devtool: don't crash on invalid utf-8. artiq_devtool: detect a race condition during connect. llvm_ir_generator: handle no-op coercions. conda: use development version of migen/misoc Revert accidentally committed code. Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623" analyses.invariant_detection: implement (#622). Fix whitespace. coredevice.dds: work around the round(numpy.float64()) snafu. coredevice.dds: update from obsolete int(width=) syntax (fixes #621). ...
* phaser: (23 commits) RELEASE_NOTES: update pipistrello: add some inputs Remove last vestiges of nist_qc1. Fully drop AD9858 and kc705-nist_qc1 support (closes #576). coredevice.dds: reimplement fully in ARTIQ Python. compiler: unbreak casts to int32/int64. analyses.constness: fix false positive on x[...]. inferencer: significantly improve the op-assignment diagnostic. Fix tests. Move mu_to_seconds, seconds_to_mu to Core. artiq_devtool: don't crash on invalid utf-8. artiq_devtool: detect a race condition during connect. llvm_ir_generator: handle no-op coercions. conda: use development version of migen/misoc Revert accidentally committed code. Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623" analyses.invariant_detection: implement (#622). Fix whitespace. coredevice.dds: work around the round(numpy.float64()) snafu. coredevice.dds: update from obsolete int(width=) syntax (fixes #621). ...
@sbourdeauducq I was thinking of submitting a patch for the nist_qc2 gateware as well. Why does the timing fail in 3.0 exactly? |
Failing timing is a regular, semi-random and annoying problem with FPGA tools. I didn't keep the Vivado timing report, you can run the synthesis again to get it and see where the critical paths are in the design. |
I've had to increase the RTIO FIFO depths in the NIST_CLOCK gateware in order to get my sideband cooling pulse sequence to run without underflow errors. Could you please incorporate the changes in the diff below so that I don't have to continue compiling my own gateware in the future? (I'm not aware of anyone else using the NIST_CLOCK gateware, so I don't think this would adversely affect anyone. If I'm wrong, please comment here.)
nist_clock_fifo_patch.txt
For reference, even with my increased FIFO depths the block ram usage is only 47%.
As an aside, I know that @r-srinivas is doing the same thing for NIST_QC2 (see #530), so it might be convenient to him to change those FIFO depths also.
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