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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Nov 20, 2016

  1. Revert "fhdl.verilog: escape names not starting with [a-zA-Z_]."

    This reverts commit a3cc612.
    whitequark committed Nov 20, 2016
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    a23224a View commit details
  2. fhdl.structure: reject signal names that aren't valid Python identifi…

    …ers.
    
    Such signal names are unergonomic to use and will cause problems
    downstream, such as in fhdl.verilog.
    whitequark committed Nov 20, 2016
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    51c23b8 View commit details
Showing with 22 additions and 25 deletions.
  1. +6 −6 migen/build/platforms/de0cv.py
  2. +9 −1 migen/fhdl/structure.py
  3. +7 −18 migen/fhdl/verilog.py
12 changes: 6 additions & 6 deletions migen/build/platforms/de0cv.py
Original file line number Diff line number Diff line change
@@ -27,12 +27,12 @@
("user_led", 9, Pins("L1"), IOStandard("3.3-V LVTTL")),


("7seg", 0, Pins("U21 V21 W22 W21 Y22 Y21 AA22"), IOStandard("3.3-V LVTTL")),
("7seg", 1, Pins("AA20 AB20 AA19 AA18 AB18 AA17 U22"), IOStandard("3.3-V LVTTL")),
("7seg", 2, Pins("Y19 AB17 AA10 Y14 V14 AB22 AB21"), IOStandard("3.3-V LVTTL")),
("7seg", 3, Pins("Y16 W16 Y17 V16 U17 V18 V19"), IOStandard("3.3-V LVTTL")),
("7seg", 4, Pins("U20 Y20 V20 U16 U15 Y15 P9"), IOStandard("3.3-V LVTTL")),
("7seg", 5, Pins("N9 M8 T14 P14 C1 C2 W19"), IOStandard("3.3-V LVTTL")),
("seven_seg", 0, Pins("U21 V21 W22 W21 Y22 Y21 AA22"), IOStandard("3.3-V LVTTL")),
("seven_seg", 1, Pins("AA20 AB20 AA19 AA18 AB18 AA17 U22"), IOStandard("3.3-V LVTTL")),
("seven_seg", 2, Pins("Y19 AB17 AA10 Y14 V14 AB22 AB21"), IOStandard("3.3-V LVTTL")),
("seven_seg", 3, Pins("Y16 W16 Y17 V16 U17 V18 V19"), IOStandard("3.3-V LVTTL")),
("seven_seg", 4, Pins("U20 Y20 V20 U16 U15 Y15 P9"), IOStandard("3.3-V LVTTL")),
("seven_seg", 5, Pins("N9 M8 T14 P14 C1 C2 W19"), IOStandard("3.3-V LVTTL")),


("key", 0, Pins("U7"), IOStandard("3.3-V LVTTL")),
10 changes: 9 additions & 1 deletion migen/fhdl/structure.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
import builtins as _builtins
import collections as _collections
import re as _re

from migen.fhdl import tracer as _tracer
from migen.util.misc import flat_iteration as _flat_iteration
@@ -313,11 +314,18 @@ class Signal(_Value):
related : Signal or None
attr : set of synthesis attributes
"""
_name_re = _re.compile(r"^[a-zA-Z_]+$")

def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None, attr=None):
from migen.fhdl.bitcontainer import bits_for

_Value.__init__(self)

for n in [name, name_override]:
if n is not None and not self._name_re.match(n):
raise ValueError("Signal name {} is not a valid Python identifier"
.format(repr(n)))

# determine number of bits and signedness
if bits_sign is None:
if min is None:
@@ -532,7 +540,7 @@ def __init__(self, test, cases):
for k, v in cases.items():
if isinstance(k, (bool, int)):
k = Constant(k)
if (not isinstance(k, Constant)
if (not isinstance(k, Constant)
and not (isinstance(k, str) and k == "default")):
raise TypeError("Case object is not a Migen constant")
if not isinstance(v, _collections.Iterable):
25 changes: 7 additions & 18 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
from functools import partial
from operator import itemgetter
import collections
import re

from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
@@ -32,24 +31,14 @@
}


_name_re = re.compile("^[a-zA-Z_]")

def _printname(ns, s):
n = ns.get_name(s)
if _name_re.match(n):
return n
else:
return "\\" + n + " "


def _printsig(ns, s):
if s.signed:
n = "signed "
else:
n = ""
if len(s) > 1:
n += "[" + str(len(s)-1) + ":0] "
n += _printname(ns, s)
n += ns.get_name(s)
return n


@@ -65,7 +54,7 @@ def _printexpr(ns, node):
if isinstance(node, Constant):
return _printconstant(node)
elif isinstance(node, Signal):
return _printname(ns, node), node.signed
return ns.get_name(node), node.signed
elif isinstance(node, _Operator):
arity = len(node.operands)
r1, s1 = _printexpr(ns, node.operands[0])
@@ -257,7 +246,7 @@ def _printcomb(f, ns,
r += explanation
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"
r += "initial " + _printname(ns, dummy_s) + " <= 1'd0;\n"
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
r += syn_on
r += "\n"

@@ -278,15 +267,15 @@ def _printcomb(f, ns,
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
if blocking_assign:
for t in g[0]:
r += "\t" + _printname(ns, t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_BLOCKING, 1, g[1])
else:
for t in g[0]:
r += "\t" + _printname(ns, t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
if dummy_signal:
r += syn_off
r += "\t" + _printname(ns, dummy_d) + " <= " + _printname(ns, dummy_s) + ";\n"
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
r += "end\n"
r += "\n"
@@ -296,7 +285,7 @@ def _printcomb(f, ns,
def _printsync(f, ns):
r = ""
for k, v in sorted(f.sync.items(), key=itemgetter(0)):
r += "always @(posedge " + _printname(ns, f.clock_domains[k].clk) + ") begin\n"
r += "always @(posedge " + ns.get_name(f.clock_domains[k].clk) + ") begin\n"
r += _printnode(ns, _AT_SIGNAL, 1, v)
r += "end\n\n"
return r