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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 0e76cbc4147e
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Nov 9, 2016

  1. conda: use pythonparser 1.0.

    whitequark committed Nov 9, 2016
    Copy the full SHA
    67e743d View commit details

Commits on Nov 10, 2016

  1. artiq_compile: actually disable attribute writeback.

    I wrote both halves of this condition but forgot to hook
    them together.
    
    Fixes #586.
    whitequark committed Nov 10, 2016
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    0e76cbc View commit details
Showing with 10 additions and 6 deletions.
  1. +4 −2 artiq/compiler/module.py
  2. +4 −2 artiq/coredevice/core.py
  3. +1 −1 artiq/frontend/artiq_compile.py
  4. +1 −1 conda/artiq/meta.yaml
6 changes: 4 additions & 2 deletions artiq/compiler/module.py
Original file line number Diff line number Diff line change
@@ -40,7 +40,8 @@ def from_filename(cls, filename, engine=None):
return cls(source.Buffer(f.read(), filename, 1), engine=engine)

class Module:
def __init__(self, src, ref_period=1e-6):
def __init__(self, src, ref_period=1e-6, attribute_writeback=True):
self.attribute_writeback = attribute_writeback
self.engine = src.engine
self.embedding_map = src.embedding_map
self.name = src.name
@@ -79,7 +80,8 @@ def build_llvm_ir(self, target):
llvm_ir_generator = transforms.LLVMIRGenerator(
engine=self.engine, module_name=self.name, target=target,
embedding_map=self.embedding_map)
return llvm_ir_generator.process(self.artiq_ir, attribute_writeback=True)
return llvm_ir_generator.process(self.artiq_ir,
attribute_writeback=self.attribute_writeback)

def __repr__(self):
printer = types.TypePrinter()
6 changes: 4 additions & 2 deletions artiq/coredevice/core.py
Original file line number Diff line number Diff line change
@@ -81,15 +81,17 @@ def __init__(self, dmgr, ref_period, external_clock=False,
self.core = self
self.comm.core = self

def compile(self, function, args, kwargs, set_result=None, with_attr_writeback=True):
def compile(self, function, args, kwargs, set_result=None, attribute_writeback=True):
try:
engine = _DiagnosticEngine(all_errors_are_fatal=True)

stitcher = Stitcher(engine=engine, core=self, dmgr=self.dmgr)
stitcher.stitch_call(function, args, kwargs, set_result)
stitcher.finalize()

module = Module(stitcher, ref_period=self.ref_period)
module = Module(stitcher,
ref_period=self.ref_period,
attribute_writeback=attribute_writeback)
target = OR1KTarget()

library = target.compile_and_link([module])
2 changes: 1 addition & 1 deletion artiq/frontend/artiq_compile.py
Original file line number Diff line number Diff line change
@@ -55,7 +55,7 @@ def main():

object_map, kernel_library, _, _ = \
core.compile(exp.run, [exp_inst], {},
with_attr_writeback=False)
attribute_writeback=False)
except CompileError as error:
return
finally:
2 changes: 1 addition & 1 deletion conda/artiq/meta.yaml
Original file line number Diff line number Diff line change
@@ -37,7 +37,7 @@ requirements:
- pygit2
- aiohttp
- binutils-or1k-linux
- pythonparser 0.0 py_6
- pythonparser 1.0
- levenshtein

test: