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kc705: use misoc clock for false path
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sbourdeauducq committed Oct 30, 2016
1 parent cd68577 commit 2392113
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -149,7 +149,7 @@ def add_rtio(self, rtio_channels):
self.rtio_crg.cd_rtio.clk.attr.add("keep")
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_false_path_constraints(
self.rtio.cd_rsys.clk,
self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)

self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,

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