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replace synthesis pseudo-comments with V2001 attributes
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Original file line number | Diff line number | Diff line change |
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@@ -1,23 +1,12 @@ | ||
from migen import * | ||
from migen.fhdl.specials import SynthesisDirective | ||
from migen.build.xilinx.common import XilinxMultiReg | ||
from migen.build.xilinx.vivado import XilinxVivadoToolchain | ||
from migen.fhdl import verilog | ||
from migen.genlib.cdc import * | ||
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class XilinxMultiRegImpl(MultiRegImpl): | ||
def __init__(self, *args, **kwargs): | ||
MultiRegImpl.__init__(self, *args, **kwargs) | ||
self.specials += set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r) | ||
for r in self.regs) | ||
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class XilinxMultiReg: | ||
@staticmethod | ||
def lower(dr): | ||
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n) | ||
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if __name__ == "__main__": | ||
ps = PulseSynchronizer("from", "to") | ||
v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg}) | ||
v = verilog.convert(ps, {ps.i, ps.o}, | ||
special_overrides={MultiReg: XilinxMultiReg}, | ||
attr_translate=XilinxVivadoToolchain.attr_translate) | ||
print(v) |
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