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kc705: add Ethernet clock constraints
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sbourdeauducq committed Oct 29, 2016
1 parent 3e52b91 commit 4926228
Showing 1 changed file with 9 additions and 0 deletions.
9 changes: 9 additions & 0 deletions misoc/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -121,6 +121,15 @@ def __init__(self, *args, **kwargs):
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

self.crg.cd_sys.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)

def soc_kc705_args(parser):
soc_sdram_args(parser)

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