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kc705: clean up clock constraints
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sbourdeauducq committed Oct 29, 2016
1 parent ed4d57c commit c656a53
Showing 1 changed file with 1 addition and 10 deletions.
11 changes: 1 addition & 10 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -146,20 +146,11 @@ def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")

self.rtio.cd_rsys.clk.attr.add("keep")
self.rtio_crg.cd_rtio.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")

self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
self.platform.add_false_path_constraints(
self.rtio.cd_rsys.clk,
self.rtio_crg.cd_rtio.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
self.rtio_crg.cd_rtio.clk)

self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if())

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