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kc705: automatic Ethernet TX clock constraint
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sbourdeauducq committed Oct 29, 2016
1 parent a361611 commit d1c5252
Showing 1 changed file with 4 additions and 0 deletions.
4 changes: 4 additions & 0 deletions migen/build/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -502,6 +502,10 @@ def do_finalize(self, fragment):
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:

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