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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 988cbd3dbfc3
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Oct 29, 2016

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    ca5ee58 View commit details
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    988cbd3 View commit details
Showing with 11 additions and 0 deletions.
  1. +3 −0 migen/build/xilinx/platform.py
  2. +8 −0 migen/build/xilinx/vivado.py
3 changes: 3 additions & 0 deletions migen/build/xilinx/platform.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
from migen.fhdl.specials import Keep
from migen.build.generic_platform import GenericPlatform
from migen.build.xilinx import common, vivado, ise

@@ -18,6 +19,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.xilinx_special_overrides)
if self.device[:3] == "xc7":
so.update(common.xilinx_s7_special_overrides)
if isinstance(self.toolchain, vivado.XilinxVivadoToolchain):
so[Keep] = vivado.VivadoKeep
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

8 changes: 8 additions & 0 deletions migen/build/xilinx/vivado.py
Original file line number Diff line number Diff line change
@@ -6,6 +6,7 @@
import sys

from migen.fhdl.structure import _Fragment
from migen.fhdl.specials import SynthesisDirective
from migen.build.generic_platform import *
from migen.build import tools
from migen.build.xilinx import common
@@ -70,6 +71,13 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
raise OSError("Subprocess failed")


class VivadoKeep:
@staticmethod
def emit_verilog(directive, ns, add_data_file):
sig_name = ns.get_name(directive.signals["s"])
return "// synthesis attribute dont_touch of " + sig_name + " is true\n"


class XilinxVivadoToolchain:
def __init__(self):
self.bitstream_commands = []