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drtio: simpler link layer
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sbourdeauducq committed Nov 17, 2016
1 parent 09363e1 commit bb047aa
Showing 7 changed files with 171 additions and 241 deletions.
9 changes: 4 additions & 5 deletions artiq/gateware/drtio/core.py
Original file line number Diff line number Diff line change
@@ -6,10 +6,9 @@


class DRTIOSatellite(Module):
def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63,
ll_rx_ready_confirm=1000):
def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63):
self.submodules.link_layer = link_layer.LinkLayer(
transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
transceiver.encoder, transceiver.decoders)
self.comb += [
transceiver.rx_reset.eq(self.link_layer.rx_reset),
self.link_layer.rx_ready.eq(transceiver.rx_ready)
@@ -52,9 +51,9 @@ def get_csrs(self):


class DRTIOMaster(Module):
def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000):
def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
self.submodules.link_layer = link_layer.LinkLayer(
transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
transceiver.encoder, transceiver.decoders)
self.comb += [
transceiver.rx_reset.eq(self.link_layer.rx_reset),
self.link_layer.rx_ready.eq(transceiver.rx_ready)
339 changes: 150 additions & 189 deletions artiq/gateware/drtio/link_layer.py

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion artiq/gateware/drtio/transceiver/gtx_7series.py
Original file line number Diff line number Diff line change
@@ -185,7 +185,7 @@ def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
self.decoders[1].input.eq(rxdata[10:])
]

clock_aligner = BruteforceClockAligner(0b0001111100, self.rtio_clk_freq)
clock_aligner = BruteforceClockAligner(0b0101111100, self.rtio_clk_freq)
self.submodules += clock_aligner
self.comb += [
clock_aligner.rxdata.eq(rxdata),
7 changes: 5 additions & 2 deletions artiq/runtime.rs/src/drtio.rs
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@ use sched::{Waiter, Spawner};

fn drtio_link_is_up() -> bool {
unsafe {
csr::drtio::link_status_read() == 5
csr::drtio::link_status_read() == 1
}
}

@@ -31,7 +31,10 @@ fn drtio_init_channel(channel: u16) {
pub fn link_thread(waiter: Waiter, _spawner: Spawner) {
loop {
waiter.until(drtio_link_is_up).unwrap();
info!("link is up");
info!("link RX is up");

waiter.sleep(300);
info!("wait for remote side done");

drtio_sync_tsc();
info!("TSC synced");
8 changes: 1 addition & 7 deletions artiq/test/gateware/drtio/test_aux_controller.py
Original file line number Diff line number Diff line change
@@ -44,13 +44,7 @@ def test_aux_controller(self):
dut = TB(4)

def link_init():
yield dut.link_layer.tx.link_init.eq(1)
yield
yield
yield dut.link_layer.tx.link_init.eq(0)
while not (yield dut.link_layer.rx.link_init):
yield
while (yield dut.link_layer.rx.link_init):
for i in range(8):
yield
yield dut.link_layer.ready.eq(1)

6 changes: 2 additions & 4 deletions artiq/test/gateware/drtio/test_full_stack.py
Original file line number Diff line number Diff line change
@@ -41,8 +41,7 @@ def __init__(self, nwords):
self.ttl1 = Signal()
self.transceivers = DummyTransceiverPair(nwords)

self.submodules.master = DRTIOMaster(self.transceivers.alice,
ll_rx_ready_confirm=15)
self.submodules.master = DRTIOMaster(self.transceivers.alice)

rx_synchronizer = DummyRXSynchronizer()
self.submodules.phy0 = ttl_simple.Output(self.ttl0)
@@ -52,8 +51,7 @@ def __init__(self, nwords):
rtio.Channel.from_phy(self.phy1, ofifo_depth=4)
]
self.submodules.satellite = DRTIOSatellite(
self.transceivers.bob, rx_synchronizer, rtio_channels,
ll_rx_ready_confirm=15)
self.transceivers.bob, rx_synchronizer, rtio_channels)


class TestFullStack(unittest.TestCase):
41 changes: 8 additions & 33 deletions artiq/test/gateware/drtio/test_link_layer.py
Original file line number Diff line number Diff line change
@@ -22,15 +22,6 @@ def pump():
return rseq


class TestScrambler(unittest.TestCase):
def test_roundtrip(self):
seq = list(range(256))*3
scrambled_seq = process(seq)
descrambled_seq = process(scrambled_seq)
self.assertNotEqual(seq, scrambled_seq)
self.assertEqual(seq, descrambled_seq)


class Loopback(Module):
def __init__(self, nwords):
ks = [Signal() for k in range(nwords)]
@@ -45,12 +36,9 @@ class TestLinkLayer(unittest.TestCase):
def test_packets(self):
dut = Loopback(4)

def link_init():
yield dut.tx.link_init.eq(1)
yield
yield
yield dut.tx.link_init.eq(0)
yield
def scrambler_sync():
for i in range(8):
yield

rt_packets = [
[0x12459970, 0x9938cdef, 0x12340000],
@@ -59,10 +47,7 @@ def link_init():
[0x88277475, 0x19883332, 0x19837662, 0x81726668, 0x81876261]
]
def transmit_rt_packets():
while not (yield dut.tx.link_init):
yield
while (yield dut.tx.link_init):
yield
yield from scrambler_sync()

for packet in rt_packets:
yield dut.tx.rt_frame.eq(1)
@@ -78,10 +63,7 @@ def transmit_rt_packets():
rx_rt_packets = []
@passive
def receive_rt_packets():
while not (yield dut.rx.link_init):
yield
while (yield dut.rx.link_init):
yield
yield from scrambler_sync()

previous_frame = 0
while True:
@@ -100,10 +82,7 @@ def receive_rt_packets():
[0xbb, 0xaa, 0xdd, 0xcc, 0x00, 0xff, 0xee]
]
def transmit_aux_packets():
while not (yield dut.tx.link_init):
yield
while (yield dut.tx.link_init):
yield
yield from scrambler_sync()

for packet in aux_packets:
yield dut.tx.aux_frame.eq(1)
@@ -123,10 +102,7 @@ def transmit_aux_packets():
rx_aux_packets = []
@passive
def receive_aux_packets():
while not (yield dut.rx.link_init):
yield
while (yield dut.rx.link_init):
yield
yield from scrambler_sync()

previous_frame = 0
while True:
@@ -140,8 +116,7 @@ def receive_aux_packets():
packet.append((yield dut.rx.aux_data))
yield

run_simulation(dut, [link_init(),
transmit_rt_packets(), receive_rt_packets(),
run_simulation(dut, [transmit_rt_packets(), receive_rt_packets(),
transmit_aux_packets(), receive_aux_packets()])

# print("RT:")

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