Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 0ee47e77aee3
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 04813ea29bc7
Choose a head ref
  • 4 commits
  • 5 files changed
  • 1 contributor

Commits on Nov 19, 2016

  1. 1
    Copy the full SHA
    b714137 View commit details
  2. rtio: auto clear output event data and address

    This is to support channels where variable length
    event data is well-defined through zero-padding.
    E.g. in the case of `Spline` zero-padding of events naturally
    corresponds to low-order knots.
    
    Use timestamp change as trigger. This assumes that writes to the
    timestamp register always precede address and data writes.
    It does not break support for ganged writes of the same event
    timestamp and data/address to multiple channels or
    channel-addresses.
    jordens committed Nov 19, 2016
    Copy the full SHA
    97a5404 View commit details
  3. Copy the full SHA
    e53d0bc View commit details
  4. Copy the full SHA
    04813ea View commit details
Showing with 67 additions and 46 deletions.
  1. +5 −5 artiq/examples/phaser/device_db.pyon
  2. +17 −11 artiq/gateware/dsp/sawg.py
  3. +26 −14 artiq/gateware/dsp/tools.py
  4. +10 −2 artiq/gateware/rtio/core.py
  5. +9 −14 artiq/gateware/targets/kc705.py
10 changes: 5 additions & 5 deletions artiq/examples/phaser/device_db.pyon
Original file line number Diff line number Diff line change
@@ -12,7 +12,7 @@
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {
"ref_period": 1e-9,
"ref_period": 5/6,
"external_clock": True
}
},
@@ -54,24 +54,24 @@
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 4, "parallelism": 4}
"arguments": {"channel_base": 4, "parallelism": 2}
},
"sawg1": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 7, "parallelism": 4}
"arguments": {"channel_base": 7, "parallelism": 2}
},
"sawg2": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 10, "parallelism": 4}
"arguments": {"channel_base": 10, "parallelism": 2}
},
"sawg3": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 13, "parallelism": 4}
"arguments": {"channel_base": 13, "parallelism": 2}
}
}
28 changes: 17 additions & 11 deletions artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -104,10 +104,11 @@ class Config(Module):
def __init__(self, width):
self.clr = Signal(4, reset=0b1111)
self.iq_en = Signal(2, reset=0b01)
self.limit = [[Signal((width, True), reset=-(1 << width - 1)),
self.limits = [[Signal((width, True), reset=-(1 << width - 1)),
Signal((width, True), reset=(1 << width - 1) - 1)]
for i in range(2)]
self.i = Endpoint([("addr", bits_for(4 + 2*len(self.limit))),
for i in range(3)]
self.clipped = [Signal(2) for i in range(3)] # TODO
self.i = Endpoint([("addr", bits_for(4 + len(self.limits))),
("data", 16)])
self.ce = Signal()

@@ -118,7 +119,7 @@ def __init__(self, width):
pad = Signal()

reg = Array([Cat(div, n), self.clr, self.iq_en, pad] +
sum(self.limit, []))
[Cat(*l) for l in self.limits])

self.comb += [
self.i.ack.eq(1),
@@ -161,7 +162,7 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):
self.widths = widths
self.orders = orders
self.parallelism = parallelism
self.latency = a1.latency + b.latency + 1
self.latency = a1.latency + b.latency + 2
self.cordic_gain = a1.gain*b.gain

###
@@ -172,17 +173,22 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):
b.ce.eq(cfg.ce),
u.o.ack.eq(cfg.ce),
Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
b.i.x.eq(self.sat_add([a1.xo[0], a2.xo[0]])),
b.i.y.eq(self.sat_add([a1.yo[0], a2.yo[0]])),
]
self.sync += [
b.i.x.eq(self.sat_add(a1.xo[0], a2.xo[0],
limits=cfg.limits[0],
clipped=cfg.clipped[0])),
b.i.y.eq(self.sat_add(a1.yo[0], a2.yo[0],
limits=cfg.limits[1],
clipped=cfg.clipped[1])),
eqh(du.i, u.o.a0),
]
# wire up outputs and q_{i,o} exchange
for o, x, y in zip(self.o, b.xo, self.y_in):
self.sync += [
o.eq(self.sat_add([
du.o,
Mux(cfg.iq_en[0], x, 0),
Mux(cfg.iq_en[1], y, 0)])),
o.eq(self.sat_add(
du.o, Mux(cfg.iq_en[0], x, 0), Mux(cfg.iq_en[1], y, 0),
limits=cfg.limits[2], clipped=cfg.clipped[2])),
]

def connect_y(self, buddy):
40 changes: 26 additions & 14 deletions artiq/gateware/dsp/tools.py
Original file line number Diff line number Diff line change
@@ -29,21 +29,33 @@ def eqh(a, b):


class SatAddMixin:
def sat_add(self, a):
"""Signed saturating addition mixin"""
def sat_add(self, *a, limits=None, clipped=None):
a = list(a)
# assert all(value_bits_sign(ai)[1] for ai in a)
n = max(len(ai) for ai in a)
o = log2_int(len(a), need_pow2=False)
s = Signal((n + o, True))
s0 = Signal((n, True))
z = Signal((1, True))
length = max(len(ai) for ai in a)
carry = log2_int(len(a), need_pow2=False)
full = Signal((length + carry, True))
limited = Signal((length, True))
clip = Signal(2)
if clipped is not None:
clipped.eq(clip)
self.comb += [
s.eq(reduce(add, a, z)),
s0[-1].eq(s[-1]),
If(s[-o-1:] == Replicate(s[-1], o + 1),
s0[:-1].eq(s[:n-1]),
).Else(
s0[:-1].eq(Replicate(~s[-1], n - 1)),
)
full.eq(reduce(add, a)),
]
return s0
if limits is None:
self.comb += [
If(full[-1-carry:] == Replicate(full[-1], carry + 1),
limited.eq(full),
clip.eq(0),
).Else(
limited.eq(Cat(Replicate(~full[-1], length - 1), full[-1])),
clip.eq(Cat(full[-1], ~full[-1])),
)
]
else:
self.comb += [
clip.eq(Cat(full < limits[0], full > limits[1])),
limited.eq(Array([full, limits[0], limits[1], 0])[clip]),
]
return limited
12 changes: 10 additions & 2 deletions artiq/gateware/rtio/core.py
Original file line number Diff line number Diff line change
@@ -334,9 +334,9 @@ def __init__(self, chan_sel_width,
self.chan_sel = CSRStorage(chan_sel_width)

if data_width:
self.o_data = CSRStorage(data_width)
self.o_data = CSRStorage(data_width, write_from_dev=True)
if address_width:
self.o_address = CSRStorage(address_width)
self.o_address = CSRStorage(address_width, write_from_dev=True)
self.o_timestamp = CSRStorage(full_ts_width)
self.o_we = CSR()
self.o_status = CSRStatus(5)
@@ -498,5 +498,13 @@ def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
<< fine_ts_width)
)

# Auto clear/zero pad event data
self.comb += [
self.kcsrs.o_data.dat_w.eq(0),
self.kcsrs.o_data.we.eq(self.kcsrs.o_timestamp.re),
self.kcsrs.o_address.dat_w.eq(0),
self.kcsrs.o_address.we.eq(self.kcsrs.o_timestamp.re),
]

def get_csrs(self):
return self.kcsrs.get_csrs()
23 changes: 9 additions & 14 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -397,13 +397,13 @@ def __init__(self, platform, refclk):
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,

p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
p_CLKIN1_PERIOD=4.0, p_CLKIN2_PERIOD=4.0,
p_CLKIN1_PERIOD=20/3, p_CLKIN2_PERIOD=20/3,
i_CLKIN1=0, i_CLKIN2=refclk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

# VCO @ 1GHz when using 250MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2,
# VCO @ 1.2GHz when using 150MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,

@@ -419,17 +419,17 @@ def __init__(self, platform, refclk):
self._pll_locked.status)
]
self.cd_rtio.clk.attr.add("keep")
platform.add_period_constraint(self.cd_rtio.clk, 8.)
platform.add_period_constraint(self.cd_rtio.clk, 20/3)


class AD9154JESD(Module, AutoCSR):
def __init__(self, platform):
ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
linerate = 10e9
refclk_freq = 250e6
fabric_freq = 250*1000*1000
linerate = 6e9
refclk_freq = 150e6
fabric_freq = 150*1000*1000

sync_pads = platform.request("ad9154_sync")
self.jsync = Signal()
@@ -494,16 +494,11 @@ def __init__(self, platform):

self.submodules.jesd = AD9154JESD(platform)

self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
self.sawgs = [sawg.Channel(width=16, parallelism=2) for i in range(4)]
self.submodules += self.sawgs

x = Signal()
y = Signal()
z = Signal()
self.sync.jesd += x.eq(~x), z.eq(x == y)
self.sync.rio_phy += y.eq(x)
for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
self.sync.jesd += conv.eq(Mux(z, Cat(ch.o[:2]), Cat(ch.o[2:])))
self.sync.jesd += conv.eq(Cat(ch.o))


class Phaser(MiniSoC, AMPSoC):