Skip to content

Commit 381e584

Browse files
sbourdeauducqsbourdeauducq
committedNov 19, 2016
drtio: handle link restarts at transceiver level
·
8.03.0
1 parent ba94ed8 commit 381e584

File tree

5 files changed

+16
-50
lines changed

5 files changed

+16
-50
lines changed
 

‎artiq/gateware/drtio/core.py

+3-8
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,7 @@ class DRTIOSatellite(Module):
99
def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63):
1010
self.submodules.link_layer = link_layer.LinkLayer(
1111
transceiver.encoder, transceiver.decoders)
12-
self.comb += [
13-
transceiver.rx_reset.eq(self.link_layer.rx_reset),
14-
self.link_layer.rx_ready.eq(transceiver.rx_ready)
15-
]
12+
self.comb += self.link_layer.rx_ready.eq(transceiver.rx_ready)
1613

1714
link_layer_sync = SimpleNamespace(
1815
tx_aux_frame=self.link_layer.tx_aux_frame,
@@ -54,10 +51,8 @@ class DRTIOMaster(Module):
5451
def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
5552
self.submodules.link_layer = link_layer.LinkLayer(
5653
transceiver.encoder, transceiver.decoders)
57-
self.comb += [
58-
transceiver.rx_reset.eq(self.link_layer.rx_reset),
59-
self.link_layer.rx_ready.eq(transceiver.rx_ready)
60-
]
54+
self.comb += self.link_layer.rx_ready.eq(transceiver.rx_ready)
55+
6156
self.submodules.rt_packets = rt_packets.RTPacketMaster(self.link_layer)
6257
self.submodules.rt_controller = rt_controller.RTController(
6358
self.rt_packets, channel_count, fine_ts_width)

‎artiq/gateware/drtio/link_layer.py

+11-29
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
from migen import *
55
from migen.genlib.fsm import *
6-
from migen.genlib.cdc import MultiReg, PulseSynchronizer
6+
from migen.genlib.cdc import MultiReg
77
from migen.genlib.misc import WaitTimer
88

99
from misoc.interconnect.csr import *
@@ -223,11 +223,8 @@ def __init__(self, decoders):
223223
class LinkLayer(Module, AutoCSR):
224224
def __init__(self, encoder, decoders):
225225
self.link_status = CSRStatus()
226-
self.link_reset = CSR()
227226

228-
# pulsed to reset receiver, rx_ready must immediately go low
229-
self.rx_reset = Signal()
230-
# receiver locked including comma alignment
227+
# receiver locked, comma aligned, receiving valid 8b10b symbols
231228
self.rx_ready = Signal()
232229

233230
tx = ClockDomainsRenamer("rtio")(LinkLayerTX(encoder))
@@ -251,45 +248,30 @@ def __init__(self, encoder, decoders):
251248
# # #
252249

253250
ready = Signal()
254-
reset_ps = PulseSynchronizer("sys", "rtio")
255-
done_ps = PulseSynchronizer("rtio", "sys")
256-
self.submodules += reset_ps, done_ps
257-
self.comb += reset_ps.i.eq(self.link_reset.re)
258-
self.sync += [
259-
If(done_ps.o, ready.eq(1)),
260-
If(reset_ps.i, ready.eq(0)),
261-
]
262-
self.comb += self.link_status.status.eq(ready)
263-
251+
ready_r = Signal()
252+
self.sync.rtio += ready_r.eq(ready)
264253
ready_rx = Signal()
265-
ready.attr.add("no_retiming")
266-
self.specials += MultiReg(ready, ready_rx, "rtio_rx")
254+
ready_r.attr.add("no_retiming")
255+
self.specials += MultiReg(ready_r, ready_rx, "rtio_rx")
267256
self.comb += [
268257
self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
269258
self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
270259
]
260+
self.specials += MultiReg(ready_r, self.link_status.status)
271261

272262
wait_scrambler = ClockDomainsRenamer("rtio")(WaitTimer(15))
273263
self.submodules += wait_scrambler
274264

275-
fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="RESET_RX"))
265+
fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="WAIT_RX_READY"))
276266
self.submodules += fsm
277267

278-
fsm.act("RESET_RX",
279-
self.rx_reset.eq(1),
280-
NextState("WAIT_RX_READY")
281-
)
282268
fsm.act("WAIT_RX_READY",
283-
If(self.rx_ready, NextState("WAIT_SCRAMBLER_SYNC")),
284-
If(reset_ps.o, NextState("RESET_RX"))
269+
If(self.rx_ready, NextState("WAIT_SCRAMBLER_SYNC"))
285270
)
286271
fsm.act("WAIT_SCRAMBLER_SYNC",
287272
wait_scrambler.wait.eq(1),
288-
If(wait_scrambler.done,
289-
done_ps.i.eq(1),
290-
NextState("READY")
291-
)
273+
If(wait_scrambler.done, NextState("READY"))
292274
)
293275
fsm.act("READY",
294-
If(reset_ps.o, NextState("RESET_RX"))
276+
ready.eq(1)
295277
)

‎artiq/gateware/drtio/transceiver/gtx_7series.py

+1-4
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
2020
Decoder(True)) for _ in range(2)]
2121
self.submodules += self.decoders
2222

23-
self.rx_reset = Signal()
2423
self.rx_ready = Signal()
2524

2625
# # #
@@ -49,8 +48,7 @@ def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
4948
GTXInit(self.rtio_clk_freq, True))
5049
self.submodules += tx_init, rx_init
5150
self.comb += tx_init.cplllock.eq(cplllock), \
52-
rx_init.cplllock.eq(cplllock), \
53-
rx_init.restart.eq(self.rx_reset)
51+
rx_init.cplllock.eq(cplllock)
5452

5553
txoutclk = Signal()
5654
txdata = Signal(20)
@@ -190,7 +188,6 @@ def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
190188
self.comb += [
191189
clock_aligner.rxdata.eq(rxdata),
192190
rx_init.restart.eq(clock_aligner.restart),
193-
clock_aligner.reset.eq(self.rx_reset),
194191
self.rx_ready.eq(clock_aligner.ready)
195192
]
196193

‎artiq/gateware/drtio/transceiver/gtx_7series_init.py

+1-2
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,6 @@ def __init__(self, comma, rtio_clk_freq, check_period=6e-3):
140140
self.rxdata = Signal(20)
141141
self.restart = Signal()
142142

143-
self.reset = Signal()
144143
self.ready = Signal()
145144

146145
check_max_val = ceil(check_period*rtio_clk_freq)
@@ -219,7 +218,7 @@ def __init__(self, comma, rtio_clk_freq, check_period=6e-3):
219218
fsm.act("READY",
220219
reset_check_counter.eq(1),
221220
self.ready.eq(1),
222-
If(self.reset,
221+
If(error_seen,
223222
checks_reset.i.eq(1),
224223
self.restart.eq(1),
225224
NextState("WAIT_COMMA")

‎artiq/runtime.rs/src/drtio.rs

-7
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,6 @@ fn drtio_link_is_up() -> bool {
77
}
88
}
99

10-
fn drtio_reset_link() {
11-
unsafe {
12-
csr::drtio::link_reset_write(1)
13-
}
14-
}
15-
1610
fn drtio_sync_tsc() {
1711
unsafe {
1812
csr::drtio::set_time_write(1);
@@ -72,6 +66,5 @@ pub fn error_thread(waiter: Waiter, _spawner: Spawner) {
7266
loop {
7367
waiter.until(drtio_packet_error_present).unwrap();
7468
error!("DRTIO packet error {}", drtio_get_packet_error());
75-
drtio_reset_link();
7669
}
7770
}

0 commit comments

Comments
 (0)
Please sign in to comment.