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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: a8fd697d41a1
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Nov 8, 2016

  1. Revert "Revert "Update for LLVM 3.9.""

    This reverts commit 5f59758.
    whitequark committed Nov 8, 2016
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    0d76880 View commit details
  2. artiq_run: fix bitrot in .ll/.bc runners.

    whitequark committed Nov 8, 2016
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    e029703 View commit details
  3. runtime: unbreak 453e8b7.

    Running
      rustc --cfg 'foo="1"'
    does not result in a statement of the form
      do_thing()
    to be compilex in.
    whitequark committed Nov 8, 2016
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    a8fd697 View commit details
Showing with 26 additions and 35 deletions.
  1. +1 −4 artiq/compiler/targets.py
  2. +17 −21 artiq/compiler/transforms/llvm_ir_generator.py
  3. +2 −4 artiq/frontend/artiq_run.py
  4. +5 −5 artiq/runtime.rs/libksupport/api.rs
  5. +1 −1 conda/artiq/meta.yaml
5 changes: 1 addition & 4 deletions artiq/compiler/targets.py
Original file line number Diff line number Diff line change
@@ -86,14 +86,11 @@ def target_machine(self):
llmachine = lltarget.create_target_machine(
features=",".join(["+{}".format(f) for f in self.features]),
reloc="pic", codemodel="default")
llmachine.set_verbose(True)
llmachine.set_asm_verbosity(True)
return llmachine

def optimize(self, llmodule):
llmachine = self.target_machine()
llpassmgr = llvm.create_module_pass_manager()
llmachine.target_data.add_pass(llpassmgr)
llmachine.add_analysis_passes(llpassmgr)

# Register our alias analysis passes.
llpassmgr.add_basic_alias_analysis_pass()
38 changes: 17 additions & 21 deletions artiq/compiler/transforms/llvm_ir_generator.py
Original file line number Diff line number Diff line change
@@ -37,9 +37,16 @@ def memoized(self, *args):
class DebugInfoEmitter:
def __init__(self, llmodule):
self.llmodule = llmodule
self.llsubprograms = []
self.llcompileunit = None
self.cache = {}

llident = self.llmodule.add_named_metadata('llvm.ident')
llident.add(self.emit_metadata(["ARTIQ"]))

llflags = self.llmodule.add_named_metadata('llvm.module.flags')
llflags.add(self.emit_metadata([2, "Debug Info Version", 3]))
llflags.add(self.emit_metadata([2, "Dwarf Version", 4]))

def emit_metadata(self, operands):
def map_operand(operand):
if operand is None:
@@ -67,14 +74,13 @@ def emit_file(self, source_buffer):
})

@memoize
def emit_compile_unit(self, source_buffer, llsubprograms):
def emit_compile_unit(self, source_buffer):
return self.emit_debug_info("DICompileUnit", {
"language": ll.DIToken("DW_LANG_Python"),
"file": self.emit_file(source_buffer),
"producer": "ARTIQ",
"runtimeVersion": 0,
"emissionKind": 2, # full=1, lines only=2
"subprograms": self.emit_metadata(llsubprograms)
}, is_distinct=True)

@memoize
@@ -86,21 +92,26 @@ def emit_subroutine_type(self, typ):
@memoize
def emit_subprogram(self, func, llfunc):
source_buffer = func.loc.source_buffer

if self.llcompileunit is None:
self.llcompileunit = self.emit_compile_unit(source_buffer)
llcompileunits = self.llmodule.add_named_metadata('llvm.dbg.cu')
llcompileunits.add(self.llcompileunit)

display_name = "{}{}".format(func.name, types.TypePrinter().name(func.type))
llsubprogram = self.emit_debug_info("DISubprogram", {
return self.emit_debug_info("DISubprogram", {
"name": func.name,
"linkageName": llfunc.name,
"type": self.emit_subroutine_type(func.type),
"file": self.emit_file(source_buffer),
"line": func.loc.line(),
"unit": self.llcompileunit,
"scope": self.emit_file(source_buffer),
"scopeLine": func.loc.line(),
"isLocal": func.is_internal,
"isDefinition": True,
"variables": self.emit_metadata([])
}, is_distinct=True)
self.llsubprograms.append(llsubprogram)
return llsubprogram

@memoize
def emit_loc(self, loc, scope):
@@ -110,18 +121,6 @@ def emit_loc(self, loc, scope):
"scope": scope
})

def finalize(self, source_buffer):
llident = self.llmodule.add_named_metadata('llvm.ident')
llident.add(self.emit_metadata(["ARTIQ"]))

llflags = self.llmodule.add_named_metadata('llvm.module.flags')
llflags.add(self.emit_metadata([2, "Debug Info Version", 3]))
llflags.add(self.emit_metadata([2, "Dwarf Version", 4]))

llcompile_units = self.llmodule.add_named_metadata('llvm.dbg.cu')
llcompile_units.add(self.emit_compile_unit(source_buffer, tuple(self.llsubprograms)))


class LLVMIRGenerator:
def __init__(self, engine, module_name, target, embedding_map):
self.engine = engine
@@ -410,9 +409,6 @@ def process(self, functions, attribute_writeback):
for func in functions:
self.process_function(func)

if any(functions):
self.debug_info_emitter.finalize(functions[0].loc.source_buffer)

if attribute_writeback and self.embedding_map is not None:
self.emit_attribute_writeback()

6 changes: 2 additions & 4 deletions artiq/frontend/artiq_run.py
Original file line number Diff line number Diff line change
@@ -73,17 +73,15 @@ def compile(self):
with open(self.file, "r") as f:
llmodule = llvm.parse_assembly(f.read())
llmodule.verify()
return self.target.link([self.target.assemble(llmodule)],
init_fn="__modinit__")
return self.target.link([self.target.assemble(llmodule)])


class LLVMBitcodeRunner(FileRunner):
def compile(self):
with open(self.file, "rb") as f:
llmodule = llvm.parse_bitcode(f.read())
llmodule.verify()
return self.target.link([self.target.assemble(llmodule)],
init_fn="__modinit__")
return self.target.link([self.target.assemble(llmodule)])


class DummyScheduler:
10 changes: 5 additions & 5 deletions artiq/runtime.rs/libksupport/api.rs
Original file line number Diff line number Diff line change
@@ -105,15 +105,15 @@ static mut API: &'static [(&'static str, *const ())] = &[
api!(rtio_input_timestamp),
api!(rtio_input_data),

#[cfg(rtio_dds_count)]
#[cfg(has_rtio_dds_count)]
api!(dds_init),
#[cfg(rtio_dds_count)]
#[cfg(has_rtio_dds_count)]
api!(dds_init_sync),
#[cfg(rtio_dds_count)]
#[cfg(has_rtio_dds_count)]
api!(dds_batch_enter),
#[cfg(rtio_dds_count)]
#[cfg(has_rtio_dds_count)]
api!(dds_batch_exit),
#[cfg(rtio_dds_count)]
#[cfg(has_rtio_dds_count)]
api!(dds_set),

api!(i2c_init),
2 changes: 1 addition & 1 deletion conda/artiq/meta.yaml
Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@ requirements:
- binutils-or1k-linux
run:
- python >=3.5.2
- llvmlite-artiq 0.10.0.dev py35_24
- llvmlite-artiq 0.11.0.dev py35_25
- lit
- outputcheck
- scipy