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base repository: m-labs/artiq
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base: 342b9e977ee5
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head repository: m-labs/artiq
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compare: 0ee47e77aee3
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Nov 18, 2016

  1. Copy the full SHA
    641f071 View commit details
  2. Revert "phaser: cap phy data width to 64 temporarily"

    This reverts commit 342b9e9.
    jordens committed Nov 18, 2016
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    bcde26f View commit details
  3. phaser: fix widths

    jordens committed Nov 18, 2016
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    0ee47e7 View commit details
Showing with 44 additions and 9 deletions.
  1. +7 −1 artiq/coredevice/rtio.py
  2. +3 −2 artiq/gateware/dsp/sawg.py
  3. +1 −2 artiq/gateware/rtio/phy/sawg.py
  4. +24 −4 artiq/runtime/rtio.c
  5. +9 −0 artiq/runtime/rtio.h
8 changes: 7 additions & 1 deletion artiq/coredevice/rtio.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
from artiq.language.core import syscall
from artiq.language.types import TInt64, TInt32, TNone
from artiq.language.types import TInt64, TInt32, TNone, TList


@syscall(flags={"nowrite"})
@@ -8,6 +8,12 @@ def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
raise NotImplementedError("syscall not simulated")


@syscall(flags={"nowrite"})
def rtio_output_list(time_mu: TInt64, channel: TInt32, addr: TInt32,
data: TList(TInt32)) -> TNone:
raise NotImplementedError("syscall not simulated")


@syscall(flags={"nowrite"})
def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
raise NotImplementedError("syscall not simulated")
5 changes: 3 additions & 2 deletions artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -58,7 +58,7 @@ def __init__(self, widths, orders, **kwargs):
self.submodules += p, f
self.ce = Signal(reset=1)
self.clr = Signal()
super().__init__(widths._replace(p=len(self.f.a0), f=len(self.f.a0)),
super().__init__(widths._replace(p=len(self.p.a0), f=len(self.f.a0)),
**kwargs)
self.latency += f.latency

@@ -146,7 +146,8 @@ def __init__(self, width=16, parallelism=4, widths=None, orders=None):
self.submodules.a1 = a1 = SplineParallelDDS(widths, orders)
self.submodules.a2 = a2 = SplineParallelDDS(widths, orders)
self.submodules.b = b = SplineParallelDUC(
widths, orders, parallelism=parallelism, a_delay=-a1.latency)
widths._replace(a=len(a1.xo[0])), orders,
parallelism=parallelism, a_delay=-a1.latency)
cfg = Config(widths.a)
u = Spline(width=widths.a, order=orders.a)
du = Delay(widths.a, a1.latency + b.latency - u.latency)
3 changes: 1 addition & 2 deletions artiq/gateware/rtio/phy/sawg.py
Original file line number Diff line number Diff line change
@@ -16,8 +16,7 @@ def __init__(self, *args, **kwargs):
_ChannelPHY.__init__(self, *args, **kwargs)
self.phys = []
for i in self.i:
rl = rtlink.Interface(rtlink.OInterface(
min(64, len(i.payload)))) # FIXME
rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
self.comb += [
i.stb.eq(rl.o.stb),
rl.o.busy.eq(~i.ack),
28 changes: 24 additions & 4 deletions artiq/runtime/rtio.c
Original file line number Diff line number Diff line change
@@ -58,7 +58,27 @@ void rtio_output(long long int timestamp, int channel, unsigned int addr,
#ifdef CSR_RTIO_O_ADDRESS_ADDR
rtio_o_address_write(addr);
#endif
rtio_o_data_write(data);
MMPTR(CSR_RTIO_O_DATA_ADDR) = data;
rtio_o_we_write(1);
status = rtio_o_status_read();
if(status)
rtio_process_exceptional_status(timestamp, channel, status);
}


void rtio_output_list(long long int timestamp, int channel,
unsigned int addr, struct artiq_list data)
{
int status, i;
volatile unsigned int *p = &MMPTR(CSR_RTIO_O_DATA_ADDR);

rtio_chan_sel_write(channel);
rtio_o_timestamp_write(timestamp);
#ifdef CSR_RTIO_O_ADDRESS_ADDR
rtio_o_address_write(addr);
#endif
for(i=0;i<data.length;i++)
*p++ = *data.elements++;
rtio_o_we_write(1);
status = rtio_o_status_read();
if(status)
@@ -116,7 +136,7 @@ unsigned int rtio_input_data(int channel)
}
}

data = rtio_i_data_read();
data = MMPTR(CSR_RTIO_I_DATA_ADDR);
rtio_i_re_write(1);
return data;
}
@@ -140,14 +160,14 @@ void rtio_log_va(long long int timestamp, const char *fmt, va_list args)
word <<= 8;
word |= *buf & 0xff;
if(*buf == 0) {
rtio_o_data_write(word);
MMPTR(CSR_RTIO_O_DATA_ADDR) = word;
rtio_o_we_write(1);
break;
}
buf++;
i++;
if(i == 4) {
rtio_o_data_write(word);
MMPTR(CSR_RTIO_O_DATA_ADDR) = word;
rtio_o_we_write(1);
word = 0;
i = 0;
9 changes: 9 additions & 0 deletions artiq/runtime/rtio.h
Original file line number Diff line number Diff line change
@@ -11,12 +11,21 @@
#define RTIO_I_STATUS_EMPTY 1
#define RTIO_I_STATUS_OVERFLOW 2


struct artiq_list {
int32_t length;
int32_t *elements;
};


void rtio_init(void);
long long int rtio_get_counter(void);
void rtio_log(long long int timestamp, const char *format, ...);
void rtio_log_va(long long int timestamp, const char *format, va_list args);
void rtio_output(long long int timestamp, int channel, unsigned int address,
unsigned int data);
void rtio_output_list(long long int timestamp, int channel,
unsigned int addr, struct artiq_list data);

/*
* Waits at least until timeout and returns the timestamp of the first