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verilog: fix 58126e0
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sbourdeauducq committed Nov 15, 2016
1 parent 8a1081e commit e8193b0
Showing 1 changed file with 2 additions and 1 deletion.
3 changes: 2 additions & 1 deletion migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -168,7 +168,8 @@ def _list_comb_wires(f):
def _printattr(sig, attr_translate):
r = ""
firsta = True
for attr in sorted(sig.attr):
for attr in sorted(sig.attr,
key=lambda x: ("", x) if isinstance(x, str) else x):
if isinstance(attr, tuple):
# platform-dependent attribute
attr_name, attr_value = attr

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