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base repository: m-labs/migen
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base: e45eaa45297d
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head repository: m-labs/migen
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compare: 47ef0d13904e
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 26, 2016

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    04edf17 View commit details
  2. Copy the full SHA
    47ef0d1 View commit details
Showing with 3 additions and 7 deletions.
  1. +1 −3 migen/fhdl/verilog.py
  2. +2 −4 migen/fhdl/visit.py
4 changes: 1 addition & 3 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -116,9 +116,7 @@ def _printexpr(ns, node):


def _printnode(ns, at, level, node):
if node is None:
return ""
elif isinstance(node, _Assign):
if isinstance(node, _Assign):
if at == _AT_BLOCKING:
assignment = " = "
elif at == _AT_NONBLOCKING:
6 changes: 2 additions & 4 deletions migen/fhdl/visit.py
Original file line number Diff line number Diff line change
@@ -38,7 +38,7 @@ def visit(self, node):
self.visit_clock_domains(node)
elif isinstance(node, _ArrayProxy):
self.visit_ArrayProxy(node)
elif node is not None:
else:
self.visit_unknown(node)

def visit_Constant(self, node):
@@ -140,10 +140,8 @@ def visit(self, node):
return self.visit_clock_domains(node)
elif isinstance(node, _ArrayProxy):
return self.visit_ArrayProxy(node)
elif node is not None:
return self.visit_unknown(node)
else:
return None
return self.visit_unknown(node)

def visit_Constant(self, node):
return node