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embedding: s/kernel_constant_attributes/kernel_invariants/g
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Requested in #359.
whitequark committed Apr 6, 2016
1 parent 32102bc commit 9cc9e8b
Showing 6 changed files with 13 additions and 13 deletions.
6 changes: 3 additions & 3 deletions artiq/compiler/embedding.py
Original file line number Diff line number Diff line change
@@ -137,9 +137,9 @@ def quote(self, value):
instance_type = types.TInstance("{}.{}".format(typ.__module__, typ.__qualname__),
OrderedDict())
instance_type.attributes['__objectid__'] = builtins.TInt32()
if hasattr(typ, 'kernel_constant_attributes'):
assert isinstance(typ.kernel_constant_attributes, set)
instance_type.constant_attributes = typ.kernel_constant_attributes
if hasattr(typ, 'kernel_invariants'):
assert isinstance(typ.kernel_invariants, set)
instance_type.constant_attributes = typ.kernel_invariants

constructor_type = types.TConstructor(instance_type)
constructor_type.attributes['__objectid__'] = builtins.TInt32()
2 changes: 1 addition & 1 deletion artiq/coredevice/core.py
Original file line number Diff line number Diff line change
@@ -59,7 +59,7 @@ class Core:
:param comm_device: name of the device used for communications.
"""

kernel_constant_attributes = {
kernel_invariants = {
"core", "ref_period", "coarse_ref_period", "ref_multiplier",
"external_clock",
}
6 changes: 3 additions & 3 deletions artiq/coredevice/dds.py
Original file line number Diff line number Diff line change
@@ -29,7 +29,7 @@ def dds_batch_exit() -> TNone:


class _BatchContextManager:
kernel_constant_attributes = {"core", "core_dds"}
kernel_invariants = {"core", "core_dds"}

def __init__(self, core_dds):
self.core_dds = core_dds
@@ -53,7 +53,7 @@ class CoreDDS:
phase-locked multiple of the RTIO clock.
"""

kernel_constant_attributes = {"core", "sysclk", "batch"}
kernel_invariants = {"core", "sysclk", "batch"}

def __init__(self, dmgr, sysclk, core_device="core"):
self.core = dmgr.get(core_device)
@@ -88,7 +88,7 @@ class _DDSGeneric:
:param channel: channel number of the DDS device to control.
"""

kernel_constant_attributes = {
kernel_invariants = {
"core", "core_dds", "bus_channel", "channel", "pow_width"
}

6 changes: 3 additions & 3 deletions artiq/coredevice/ttl.py
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@ class TTLOut:
:param channel: channel number
"""
kernel_constant_attributes = {"core", "channel"}
kernel_invariants = {"core", "channel"}

def __init__(self, dmgr, channel, core_device="core"):
self.core = dmgr.get(core_device)
@@ -84,7 +84,7 @@ class TTLInOut:
:param channel: channel number
"""
kernel_constant_attributes = {"core", "channel"}
kernel_invariants = {"core", "channel"}

def __init__(self, dmgr, channel, core_device="core"):
self.core = dmgr.get(core_device)
@@ -236,7 +236,7 @@ class TTLClockGen:
:param channel: channel number
"""
kernel_constant_attributes = {"core", "channel", "acc_width"}
kernel_invariants = {"core", "channel", "acc_width"}

def __init__(self, dmgr, channel, core_device="core"):
self.core = dmgr.get(core_device)
4 changes: 2 additions & 2 deletions artiq/test/coredevice/test_rtio.py
Original file line number Diff line number Diff line change
@@ -83,7 +83,7 @@ def run(self):


class PulseRate(EnvExperiment):
kernel_constant_attributes = {"core", "ttl_out"}
kernel_invariants = {"core", "ttl_out"}

def build(self):
self.setattr_device("core")
@@ -107,7 +107,7 @@ def run(self):


class PulseRateDDS(EnvExperiment):
kernel_constant_attributes = {"core", "core_dds", "dds0", "dds1"}
kernel_invariants = {"core", "core_dds", "dds0", "dds1"}

def build(self):
self.setattr_device("core")
2 changes: 1 addition & 1 deletion artiq/test/lit/embedding/error_attr_constant.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@
from artiq.language.types import *

class c:
kernel_constant_attributes = {'a'}
kernel_invariants = {'a'}

def __init__(self):
self.a = 1

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