Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 4c1a4af71e9e
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 452cbc34cb53
Choose a head ref
  • 2 commits
  • 8 files changed
  • 1 contributor

Commits on Apr 10, 2016

  1. cores/sdram_settings: simplify sdram modules

    @enjoy-digital @sbourdeauducq
    enjoy-digital authored and sbourdeauducq committed Apr 10, 2016
    Copy the full SHA
    ed0e451 View commit details

  2. cores/sdram_settings: use phy rate to convert ns values to sys_clk cy… 

    …cles (required to compute margin)
    @enjoy-digital @sbourdeauducq
    enjoy-digital authored and sbourdeauducq committed Apr 10, 2016
    Copy the full SHA
    452cbc3 View commit details
284 changes: 125 additions & 159 deletions misoc/cores/sdram_settings.py
View file
Original file line number Diff line number Diff line change
@@ -27,204 +27,170 @@ def GeomSettings(bankbits, rowbits, colbits):


class SDRAMModule:
def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
def __init__(self, clk_freq, rate):
self.clk_freq = clk_freq
self.memtype = memtype
self.rate = rate
self.geom_settings = GeomSettings(
bankbits=log2_int(geom_settings["nbanks"]),
rowbits=log2_int(geom_settings["nrows"]),
colbits=log2_int(geom_settings["ncols"]),
bankbits=log2_int(self.nbanks),
rowbits=log2_int(self.nrows),
colbits=log2_int(self.ncols),
)
self.timing_settings = TimingSettings(
tRP=self.ns(timing_settings["tRP"]),
tRCD=self.ns(timing_settings["tRCD"]),
tWR=self.ns(timing_settings["tWR"]),
tWTR=timing_settings["tWTR"],
tREFI=self.ns(timing_settings["tREFI"], False),
tRFC=self.ns(timing_settings["tRFC"])
tRP=self.ns(self.tRP),
tRCD=self.ns(self.tRCD),
tWR=self.ns(self.tWR),
tWTR=self.tWTR,
tREFI=self.ns(self.tREFI, False),
tRFC=self.ns(self.tRFC)
)

def ns(self, t, margin=True):
clk_period_ns = 1000000000/self.clk_freq
if margin:
t += clk_period_ns/2
margins = {
"1:1" : 0,
"1:2" : clk_period_ns/2,
"1:4" : 3*clk_period_ns/4
}
t += margins[self.rate]
return ceil(t/clk_period_ns)


# SDR
class IS42S16160(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 512
}
# Timings for -7 speedgrade
timing_settings = {
"tRP": 20,
"tRCD": 20,
"tWR": 20,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
memtype = "SDR"
# geometry
nbanks = 4
nrows = 8192
ncols = 512
# timings (-7 speedgrade)
tRP = 20
tRCD = 20
tWR = 20
tWTR = 2
tREFI = 64*1000*1000/8192
tRFC = 70


class MT48LC4M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 4096,
"ncols": 256
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 14,
"tWTR": 2,
"tREFI": 64*1000*1000/4096,
"tRFC": 66
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
memtype = "SDR"
# geometry
nbanks = 4
nrows = 4096
ncols = 256
# timings (-7 speedgrade)
tRP = 15
tRCD = 15
tWR = 14
tWTR = 2
tREFI = 64*1000*1000/4096
tRFC = 66


class AS4C16M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 512
}
# Timings for -6 speedgrade
timing_settings = {
"tRP": 18,
"tRCD": 18,
"tWR": 12,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 60
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
memtype = "SDR"
# geometry
nbanks = 4
nrows = 8192
ncols = 512
# timings (-6 speedgrade)
tRP = 18
tRCD = 18
tWR = 12
tWTR = 2
tREFI = 64*1000*1000/8192
tRFC = 60


# DDR
class MT46V32M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
self.timing_settings)
memtype = "DDR"
# geometry
nbanks = 4
nrows = 8192
ncols = 1024
# timings (-6 speedgrade)
tRP = 15
tRCD = 15
tWR = 15
tWTR = 2
tREFI = 64*1000*1000/8192
tRFC = 70


# LPDDR
class MT46H32M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 72
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
self.timing_settings)
memtype = "LPDDR"
# geometry
nbanks = 4
nrows = 8192
ncols = 1024
# timings
tRP = 15
tRCD = 15
tWR = 15
tWTR = 2
tREFI = 64*1000*1000/8192
tRFC = 72


# DDR2
class MT47H128M8(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 127.5
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings)
memtype = "DDR2"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
tRP = 15
tRCD = 15
tWR = 15
tWTR = 2
tREFI = 7800
tRFC = 127.5


class P3R1GE4JGF(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 8192,
"ncols": 1024
}
timing_settings = {
"tRP": 12.5,
"tRCD": 12.5,
"tWR": 15,
"tWTR": 3,
"tREFI": 7800,
"tRFC": 127.5,
}

def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings)
memtype = "DDR2"
# geometry
nbanks = 8
nrows = 8192
ncols = 1024
# timings
tRP = 12.5
tRCD = 12.5
tWR = 15
tWTR = 3
tREFI = 7800
tRFC = 127.5


# DDR3
class MT8JTF12864(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
self.timing_settings)
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
tRP = 15
tRCD = 15
tWR = 15
tWTR = 2
tREFI = 7800
tRFC = 70


class MT41J128M16(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 16384,
"ncols": 1024,
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 3,
"tREFI": 64*1000*1000/16384,
"tRFC": 260,
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
self.timing_settings)
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
tRP = 15
tRCD = 15
tWR = 15
tWTR = 3
tREFI = 64*1000*1000/16384
tRFC = 260
2 changes: 1 addition & 1 deletion misoc/targets/de0nano.py
View file
Original file line number Diff line number Diff line change
@@ -95,7 +95,7 @@ def __init__(self, **kwargs):
self.submodules.crg = _CRG(platform)

self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16160(self.clk_freq)
sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)

2 changes: 1 addition & 1 deletion misoc/targets/kc705.py
View file
Original file line number Diff line number Diff line change
@@ -91,7 +91,7 @@ def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):
self.submodules.crg = _CRG(platform)

self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq)
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)

2 changes: 1 addition & 1 deletion misoc/targets/mimasv2.py
View file
Original file line number Diff line number Diff line change
@@ -107,7 +107,7 @@ def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

sdram_module = MT46H32M16(self.clk_freq)
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
2 changes: 1 addition & 1 deletion misoc/targets/minispartan6.py
View file
Original file line number Diff line number Diff line change
@@ -75,7 +75,7 @@ def __init__(self, **kwargs):
self.submodules.crg = _CRG(platform, clk_freq)

self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(clk_freq)
sdram_module = AS4C16M16(clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)

2 changes: 1 addition & 1 deletion misoc/targets/mlabs_video.py
View file
Original file line number Diff line number Diff line change
@@ -88,7 +88,7 @@ def __init__(self, platform_name="mixxeo", **kwargs):

self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)

sdram_module = MT46V32M16(self.clk_freq)
sdram_module = MT46V32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=0,
2 changes: 1 addition & 1 deletion misoc/targets/papilio_pro.py
View file
Original file line number Diff line number Diff line change
@@ -81,7 +81,7 @@ def __init__(self, **kwargs):
self.submodules.crg = _CRG(platform, clk_freq)

self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(clk_freq)
sdram_module = MT48LC4M16(clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)

2 changes: 1 addition & 1 deletion misoc/targets/pipistrello.py
View file
Original file line number Diff line number Diff line change
@@ -108,7 +108,7 @@ def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

sdram_module = MT46H32M16(self.clk_freq)
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,