cores/sdram_phy: update S6QuarterRateDDRPHY to new migen

m-labs · Mar 29, 2016 · 42e17a4 · 42e17a4
1 parent 9fd5840
commit 42e17a4
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/misoc/cores/sdram_phy/s6ddrphy.py b/misoc/cores/sdram_phy/s6ddrphy.py
@@ -21,6 +21,7 @@
 
 from migen import *
 from migen.genlib.record import *
+from migen.fhdl.decorators import ClockDomainsRenamer
 
 from misoc.interconnect.dfi import *
 from misoc.cores import sdram_settings
@@ -399,7 +400,7 @@ def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
 class S6QuarterRateDDRPHY(Module):
     def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment)
-        self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"})
+        self.submodules += ClockDomainsRenamer("sys2x")(half_rate_phy)
 
         addressbits = len(pads.a)
         bankbits = len(pads.ba)