targets: update litex uart

timvideos · Apr 19, 2017 · 947321b · 947321b
1 parent 8e7dc58
commit 947321b
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Showing 5 changed files with 5 additions and 5 deletions.
diff --git a/targets/mimasv2/memtest.py b/targets/mimasv2/memtest.py
@@ -1,5 +1,5 @@
 from litex.soc.cores import uart
-from litex.soc.cores.uart.bridge import UARTWishboneBridge
+from litex.soc.cores.uart import UARTWishboneBridge
 
 from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker, LiteDRAMBISTCheckerScope
 

diff --git a/targets/mimasv2/scope.py b/targets/mimasv2/scope.py
@@ -1,5 +1,5 @@
 from litex.soc.cores import uart
-from litex.soc.cores.uart.bridge import UARTWishboneBridge
+from litex.soc.cores.uart import UARTWishboneBridge
 
 from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker, LiteDRAMBISTCheckerScope
 

diff --git a/targets/netv2/bridge_pcie.py b/targets/netv2/bridge_pcie.py
@@ -7,7 +7,7 @@
 from litex.soc.interconnect import wishbone
 
 from litex.soc.integration.soc_core import *
-from litex.soc.cores.uart.bridge import UARTWishboneBridge
+from litex.soc.cores.uart import UARTWishboneBridge
 from litex.soc.integration.builder import *
 
 from litepcie.phy.s7pciephy import S7PCIEPHY

diff --git a/targets/netv2/bridge_uart.py b/targets/netv2/bridge_uart.py
@@ -5,7 +5,7 @@
 from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.uart.bridge import UARTWishboneBridge
+from litex.soc.cores.uart import UARTWishboneBridge
 
 from litedram.modules import MT41J128M16
 from litedram.phy import a7ddrphy

diff --git a/targets/nexys_video/ddr3.py b/targets/nexys_video/ddr3.py
@@ -6,7 +6,7 @@
 from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.uart.bridge import UARTWishboneBridge
+from litex.soc.cores.uart import UARTWishboneBridge
 
 from litedram.modules import MT41K256M16
 from litedram.phy import a7ddrphy