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base repository: azonenberg/yosys
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base: 088f9c9cab8d
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head repository: azonenberg/yosys
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compare: 106e44f40640
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  • 4 commits
  • 4 files changed
  • 1 contributor

Commits on Mar 18, 2017

  1. Add simple EDIF test case generator and checker

    @cliffordwolf
    cliffordwolf committed Mar 18, 2017
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    1390e9a View commit details

Commits on Mar 19, 2017

  1. Fix EDIF: portRef member 0 is always the MSB bit

    @cliffordwolf
    cliffordwolf committed Mar 19, 2017
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    850f829 View commit details

  2. Add generation of logic cells to EDIF back-end runtest.py

    @cliffordwolf
    cliffordwolf committed Mar 19, 2017
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    0ac72e7 View commit details

Commits on Mar 20, 2017

  1. Add "write_smt2 -stdt" mode

    @cliffordwolf
    cliffordwolf committed Mar 20, 2017
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    106e44f View commit details
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