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base repository: azonenberg/yosys
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head repository: azonenberg/yosys
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  • 6 commits
  • 29 files changed
  • 2 contributors

Commits on Mar 28, 2017

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Commits on Apr 5, 2017

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Commits on Apr 6, 2017

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Commits on Apr 7, 2017

  1. Merge pull request YosysHQ#337 from dh73/master

    Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
    cliffordwolf authored Apr 7, 2017
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13 changes: 13 additions & 0 deletions CHANGELOG
Original file line number Diff line number Diff line change
@@ -3,6 +3,19 @@ List of major changes and improvements between releases
=======================================================


Yosys 0.7 .. Yosys ???
----------------------

* MAX10 and Cyclone IV Support
- Added initial version of metacommand "synth_intel".
- Improved write_verilog command to produce VQM netlist for Quartus Prime.
- Added support for MAX10 FPGA family synthesis.
- Added support for Cyclone IV family synthesis.
- Added example of implementation for DE2i-150 board.
- Added example of implementation for MAX10 development kit.
- Added LFSR example from Asic World.


Yosys 0.6 .. Yosys 0.7
----------------------

4 changes: 4 additions & 0 deletions examples/intel/DE2i-150/quartus_compile/de2i.qpf
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@@ -0,0 +1,4 @@
QUARTUS_VERSION = "16.1"
# Revisions

PROJECT_REVISION = "de2i"
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