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base repository: m-labs/migen
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compare: d8b55c7f06da
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 4, 2017

  1. genlib/record: add "do" to reserved_keywords

    @enjoy-digital
    enjoy-digital committed Jul 4, 2017
    Copy the full SHA
    2b063a3 View commit details

  2. genlib/record: replace leave_out param with keep and omit params in R… 

    …ecord.connect

This allows finer selection of signals when connection is partial.
    @enjoy-digital
    enjoy-digital committed Jul 4, 2017
    3
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    d8b55c7 View commit details
Showing with 23 additions and 10 deletions.
  1. +1 −1 migen/fhdl/verilog.py
  2. +22 −9 migen/genlib/record.py
2 changes: 1 addition & 1 deletion migen/fhdl/verilog.py
View file
Original file line number Diff line number Diff line change
@@ -27,7 +27,7 @@
"specify", "specparam", "strong0", "strong1", "supply0", "supply1",
"table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
"tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor"
"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do"
}


31 changes: 22 additions & 9 deletions migen/genlib/record.py
View file
Original file line number Diff line number Diff line change
@@ -131,25 +131,38 @@ def flatten(self):
def raw_bits(self):
return Cat(*self.flatten())

def connect(self, *slaves, leave_out=set()):
if isinstance(leave_out, str):
leave_out = {leave_out}
def connect(self, *slaves, keep=None, omit=None):
if keep is None:
_keep = set([f[0] for f in self.layout])
elif isinstance(keep, list):
_keep = set(keep)
else:
_keep = keep
if omit is None:
_omit = set()
elif isinstance(omit, list):
_omit = set(omit)
else:
_omit = omit

_keep = _keep - _omit

r = []
for f in self.layout:
field = f[0]
if field not in leave_out:
self_e = getattr(self, field)
if isinstance(self_e, Signal):
self_e = getattr(self, field)
if isinstance(self_e, Signal):
if field in _keep:
direction = f[2]
if direction == DIR_M_TO_S:
r += [getattr(slave, field).eq(self_e) for slave in slaves]
elif direction == DIR_S_TO_M:
r.append(self_e.eq(reduce(or_, [getattr(slave, field) for slave in slaves])))
else:
raise TypeError
else:
for slave in slaves:
r += self_e.connect(getattr(slave, field), leave_out=leave_out)
else:
for slave in slaves:
r += self_e.connect(getattr(slave, field), keep=keep, omit=omit)
return r

def connect_flat(self, *slaves):