global: replace leave_out with omit in Record.connect

m-labs · Jul 4, 2017 · e205c2e · e205c2e
1 parent 1d3fbc4
commit e205c2e
Showing 3 changed files with 8 additions and 8 deletions.
diff --git a/misoc/cores/liteeth_mini/mac/preamble.py b/misoc/cores/liteeth_mini/mac/preamble.py
@@ -52,7 +52,7 @@ def __init__(self, dw):
             self.source.last_be.eq(self.sink.last_be)
         ]
         fsm.act("COPY",
-            self.sink.connect(self.source, leave_out=set(["data", "last_be"])),
+            self.sink.connect(self.source, omit=set(["data", "last_be"])),
 
             If(self.sink.stb & self.sink.eop & self.source.ack,
                 NextState("IDLE"),
@@ -133,7 +133,7 @@ def __init__(self, dw):
             self.source.last_be.eq(self.sink.last_be)
         ]
         fsm.act("COPY",
-            self.sink.connect(self.source, leave_out=set(["data", "last_be"])),
+            self.sink.connect(self.source, omit=set(["data", "last_be"])),
             If(self.source.stb & self.source.eop & self.source.ack,
                 NextState("IDLE"),
             )

diff --git a/misoc/cores/sdram_phy/s6ddrphy.py b/misoc/cores/sdram_phy/s6ddrphy.py
@@ -451,14 +451,14 @@ def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         # DFI adaptation
 
         # Commands and writes
-        dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"])
+        dfi_omit = set(["rddata", "rddata_valid", "wrdata_en"])
         self.comb += [
             If(~phase_sel,
-                self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
-                self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
+                self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
+                self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
             ).Else(
-                self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
-                self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
+                self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
+                self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
             ),
         ]
         wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel

diff --git a/misoc/cores/tmpu.py b/misoc/cores/tmpu.py
@@ -49,7 +49,7 @@ def __init__(self, input_bus, page_size=4096):
                (page == self.prog_address.storage), error.eq(1))
         ]
         self.comb += [
-            input_bus.connect(self.output_bus, leave_out={"ack", "err"}),
+            input_bus.connect(self.output_bus, omit={"ack", "err"}),
             If(error,
                 input_bus.ack.eq(0),
                 input_bus.err.eq(self.output_bus.ack | self.output_bus.err)