integration: add support for memory groups

m-labs · Jul 15, 2017 · 4d9d232 · 4d9d232
1 parent bba206f
commit 4d9d232
Showing 3 changed files with 29 additions and 3 deletions.
diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py
@@ -87,6 +87,7 @@ def add_software_package(self, name, src_dir=None):
     def _generate_includes(self):
         cpu_type = self.soc.cpu_type
         memory_regions = self.soc.get_memory_regions()
+        memory_groups = self.soc.get_memory_groups()
         flash_boot_address = getattr(self.soc, "flash_boot_address", None)
         csr_regions = self.soc.get_csr_regions()
         csr_groups = self.soc.get_csr_groups()
@@ -122,7 +123,7 @@ def define(k, v):
             f.write(cpu_interface.get_csr_header(csr_regions, constants))
 
         with WriteGenerated(generated_dir, "mem.rs") as f:
-            f.write(cpu_interface.get_mem_rust(memory_regions, flash_boot_address))
+            f.write(cpu_interface.get_mem_rust(memory_regions, memory_groups, flash_boot_address))
         with WriteGenerated(generated_dir, "csr.rs") as f:
             f.write(cpu_interface.get_csr_rust(csr_regions, csr_groups, constants))
         with WriteGenerated(generated_dir, "rust-cfg") as f:

diff --git a/misoc/integration/cpu_interface.py b/misoc/integration/cpu_interface.py
@@ -44,7 +44,7 @@ def get_mem_header(regions, flash_boot_address):
     return r
 
 
-def get_mem_rust(regions, flash_boot_address):
+def get_mem_rust(regions, groups, flash_boot_address):
     r  = "// Include this file as:\n"
     r += "//     include!(concat!(env!(\"BUILDINC_DIRECTORY\"), \"/generated/mem.rs\"));\n"
     r += "#[allow(dead_code)]\n"
@@ -54,9 +54,27 @@ def get_mem_rust(regions, flash_boot_address):
             format(name=name.upper(), base=base)
         r += "  pub const {name}_SIZE: usize = 0x{size:08x};\n\n". \
             format(name=name.upper(), size=size)
+
+    if groups:
+        r += "  pub struct MemoryRegion {\n"
+        r += "    pub base: usize,\n"
+        r += "    pub size: usize,\n"
+        r += "  }\n\n"
+
+        for group_name, group_members in groups:
+            r += ("  pub static " + group_name.upper() +
+                  ": [MemoryRegion; " + str(len(group_members)) + "] = [\n")
+            for member in group_members:
+                r += "    MemoryRegion { "
+                r += "base: "+member.upper()+"_BASE, "
+                r += "size: "+member.upper()+"_SIZE, "
+                r += "},\n"
+            r += "  ];\n\n"
+
     if flash_boot_address is not None:
         r += "  pub const FLASH_BOOT_ADDRESS: usize = 0x{:08x};\n\n". \
             format(flash_boot_address)
+
     r += "}\n"
     return r
 
@@ -229,7 +247,7 @@ def get_csr_rust(regions, groups, constants):
                 r += "    pub " + csr.name + "_read: fn() -> " + rstype + ",\n"
                 if not is_readonly(csr):
                     r += "    pub " + csr.name + "_write: fn(" + rstype + "),\n";
-            r += "  };\n\n"
+            r += "  }\n\n"
 
             r += ("  pub static " + group_name.upper() +
                   ": [" + struct_name + "; " + str(len(group_members)) + "] = [\n")

diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py
@@ -63,6 +63,7 @@ def __init__(self, platform, clk_freq,
             "timer0",
             "tmpu"
         ]
+        self._memory_groups = []  # list of (group_name, (group_member0, group_member1, ...))
         self._csr_groups = []  # list of (group_name, (group_member0, group_member1, ...))
         self.interrupt_devices = []
 
@@ -125,6 +126,9 @@ def add_wb_slave(self, origin, length, interface):
     def add_memory_region(self, name, origin, length):
         self._memory_regions.append((name, origin, length))
 
+    def add_memory_group(self, group_name, members):
+        self._memory_groups.append((group_name, members))
+
     def register_mem(self, name, origin, length, interface):
         self.add_wb_slave(origin, length, interface)
         self.add_memory_region(name, origin, length)
@@ -138,6 +142,9 @@ def register_rom(self, interface, rom_size=0xa000):
     def get_memory_regions(self):
         return self._memory_regions
 
+    def get_memory_groups(self):
+        return self._memory_groups
+
     def check_csr_region(self, name, origin):
         for n, o, l, obj in self._csr_regions:
             if n == name or o == origin: