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azonenbergazonenberg
committedJun 20, 2017
XC2C model: implemented PLA AND array
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Diff for: ‎hdl/xc2c-model/XC2CAndArray.v

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Original file line numberDiff line numberDiff line change
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`default_nettype none
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/***********************************************************************************************************************
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* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
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* *
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* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
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* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
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* any later version. *
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* *
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* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
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* more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
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* find one here: *
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* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
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* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
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**********************************************************************************************************************/
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module XC2CAndArray(zia_in, config_bits, pterm_out);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// No configuration, all AND arrays are the same.
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// Differences in bitstream ordering, if any, are handled by XC2CDevice
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// I/Os
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input wire[39:0] zia_in;
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input wire[80*56 - 1 : 0] config_bits;
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output reg[55:0] pterm_out;
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Shuffle the config bits back to their proper 2D form
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integer nterm;
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integer nrow;
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integer nin;
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reg[79:0] and_config[55:0];
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always @(*) begin
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for(nterm=0; nterm<56; nterm=nterm+1) begin
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for(nin=0; nin<80; nin=nin + 1)
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and_config[nterm][nin] <= config_bits[nterm*80 + nin];
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// The actual AND array
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//Higher value is X, lower is !X
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always @(*) begin
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for(nterm=0; nterm<56; nterm = nterm+1) begin
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pterm_out[nterm] = 1; //default if no terms selected
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//AND in the ZIA stuff
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for(nrow=0; nrow<40; nrow=nrow+1) begin
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if(!and_config[nterm][nrow*2])
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pterm_out[nterm] = pterm_out[nterm] & zia_in[nrow];
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if(!and_config[nterm][nrow*2 + 1])
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pterm_out[nterm] = pterm_out[nterm] & !zia_in[nrow];
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end
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end
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end
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endmodule

Diff for: ‎hdl/xc2c-model/XC2CDevice.v

+22-17
Original file line numberDiff line numberDiff line change
@@ -168,8 +168,8 @@ module XC2CDevice(
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//TODO: pipeline this or are we OK in one cycle?
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//If we go multicycle, how do we handle this with no clock? Real chip is self-timed internally
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if(config_erase) begin
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for(i=0; i<MEM_DEPTH; i=i+1)
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ram_bitstream[i] <= {SHREG_WIDTH{1'b1}};
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for(row=0; row<MEM_DEPTH; row=row+1)
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ram_bitstream[row] <= {SHREG_WIDTH{1'b1}};
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end
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end
@@ -256,8 +256,8 @@ module XC2CDevice(
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// PLA AND array
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reg[56*80-1:0] left_and_config;
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reg[56*80-1:0] right_and_config;
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reg[80*56-1:0] left_and_config;
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reg[80*56-1:0] right_and_config;
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wire[55:0] left_pterms;
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wire[55:0] right_pterms;
@@ -277,24 +277,33 @@ module XC2CDevice(
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);
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//Hook up the config bits
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integer nterm;
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always @(*) begin
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for(row=0; row<40; row=row+1) begin
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//We have stuff at the top and bottom of array, with OR array in the middle
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//Left side: 249:138
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//Right side: 121:10 (mirrored)
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//Each row is two bits from PT0, two from PT1, two from PT2, etc
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//Right side: 249:138 (mirrored)
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//Left side: 121:10
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if(row >= 20) begin
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for(nbit=0; nbit<112; nbit=nbit+1) begin
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right_and_config[row*112 + nbit] <= ram_bitstream[row-8][138 + nbit];
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left_and_config[row*112 + nbit] <= ram_bitstream[row-8][121 - nbit];
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for(nterm=0; nterm<56; nterm=nterm+1) begin
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right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row-8][249 - nterm*2 - 1];
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right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row-8][249 - nterm*2 - 0];
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left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row-8][10 + nterm*2 + 0];
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left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row-8][10 + nterm*2 + 1];
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end
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end
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else begin
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for(nbit=0; nbit<112; nbit=nbit+1) begin
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right_and_config[row*112 + nbit] <= ram_bitstream[row][138 + nbit];
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left_and_config[row*112 + nbit] <= ram_bitstream[row][121 - nbit];
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for(nterm=0; nterm<56; nterm=nterm+1) begin
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right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
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right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];
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left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
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left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
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end
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end
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@@ -313,11 +322,7 @@ module XC2CDevice(
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//Drive all unused outputs to 0, then hook up our outputs
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//Should be X, !X, X, X
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assign iob_out[31:7] = 25'h0;
316-
//assign iob_out[6:3] = {right_pterms[19], right_pterms[22], right_pterms[25], right_pterms[28]};
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assign iob_out[6] = &right_pterms;
318-
assign iob_out[5] = &left_pterms;
319-
assign iob_out[4] = &left_and_config[19*80 +: 80];
320-
assign iob_out[3] = &right_and_config[19*80 +: 80];
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assign iob_out[6:3] = {right_pterms[19], right_pterms[22], right_pterms[25], right_pterms[28]};
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assign iob_out[2:0] = 3'h0;
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endmodule

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