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XC2C model: implemented PLA AND array
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azonenberg committed Jun 20, 2017
1 parent e0cd3cc commit 3995978
Showing 2 changed files with 87 additions and 17 deletions.
65 changes: 65 additions & 0 deletions hdl/xc2c-model/XC2CAndArray.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,65 @@
`default_nettype none
/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
module XC2CAndArray(zia_in, config_bits, pterm_out);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// No configuration, all AND arrays are the same.
// Differences in bitstream ordering, if any, are handled by XC2CDevice

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/Os

input wire[39:0] zia_in;
input wire[80*56 - 1 : 0] config_bits;
output reg[55:0] pterm_out;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Shuffle the config bits back to their proper 2D form

integer nterm;
integer nrow;
integer nin;

reg[79:0] and_config[55:0];
always @(*) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
for(nin=0; nin<80; nin=nin + 1)
and_config[nterm][nin] <= config_bits[nterm*80 + nin];
end
end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual AND array

//Higher value is X, lower is !X
always @(*) begin
for(nterm=0; nterm<56; nterm = nterm+1) begin
pterm_out[nterm] = 1; //default if no terms selected

//AND in the ZIA stuff
for(nrow=0; nrow<40; nrow=nrow+1) begin
if(!and_config[nterm][nrow*2])
pterm_out[nterm] = pterm_out[nterm] & zia_in[nrow];
if(!and_config[nterm][nrow*2 + 1])
pterm_out[nterm] = pterm_out[nterm] & !zia_in[nrow];
end
end
end

endmodule
39 changes: 22 additions & 17 deletions hdl/xc2c-model/XC2CDevice.v
Original file line number Diff line number Diff line change
@@ -168,8 +168,8 @@ module XC2CDevice(
//TODO: pipeline this or are we OK in one cycle?
//If we go multicycle, how do we handle this with no clock? Real chip is self-timed internally
if(config_erase) begin
for(i=0; i<MEM_DEPTH; i=i+1)
ram_bitstream[i] <= {SHREG_WIDTH{1'b1}};
for(row=0; row<MEM_DEPTH; row=row+1)
ram_bitstream[row] <= {SHREG_WIDTH{1'b1}};
end

end
@@ -256,8 +256,8 @@ module XC2CDevice(
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PLA AND array

reg[56*80-1:0] left_and_config;
reg[56*80-1:0] right_and_config;
reg[80*56-1:0] left_and_config;
reg[80*56-1:0] right_and_config;

wire[55:0] left_pterms;
wire[55:0] right_pterms;
@@ -277,24 +277,33 @@ module XC2CDevice(
);

//Hook up the config bits
integer nterm;
always @(*) begin

for(row=0; row<40; row=row+1) begin

//We have stuff at the top and bottom of array, with OR array in the middle
//Left side: 249:138
//Right side: 121:10 (mirrored)
//Each row is two bits from PT0, two from PT1, two from PT2, etc

//Right side: 249:138 (mirrored)
//Left side: 121:10
if(row >= 20) begin
for(nbit=0; nbit<112; nbit=nbit+1) begin
right_and_config[row*112 + nbit] <= ram_bitstream[row-8][138 + nbit];
left_and_config[row*112 + nbit] <= ram_bitstream[row-8][121 - nbit];
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row-8][249 - nterm*2 - 1];
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row-8][249 - nterm*2 - 0];

left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row-8][10 + nterm*2 + 0];
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row-8][10 + nterm*2 + 1];
end
end

else begin
for(nbit=0; nbit<112; nbit=nbit+1) begin
right_and_config[row*112 + nbit] <= ram_bitstream[row][138 + nbit];
left_and_config[row*112 + nbit] <= ram_bitstream[row][121 - nbit];
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];

left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
end
end

@@ -313,11 +322,7 @@ module XC2CDevice(
//Drive all unused outputs to 0, then hook up our outputs
//Should be X, !X, X, X
assign iob_out[31:7] = 25'h0;
//assign iob_out[6:3] = {right_pterms[19], right_pterms[22], right_pterms[25], right_pterms[28]};
assign iob_out[6] = &right_pterms;
assign iob_out[5] = &left_pterms;
assign iob_out[4] = &left_and_config[19*80 +: 80];
assign iob_out[3] = &right_and_config[19*80 +: 80];
assign iob_out[6:3] = {right_pterms[19], right_pterms[22], right_pterms[25], right_pterms[28]};
assign iob_out[2:0] = 3'h0;

endmodule

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