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azonenbergazonenberg
committedJun 21, 2017
Initial skeleton of macrocell code. Has correct bitstream values loaded, but largely ignored
1 parent 73a1180 commit f1282b2

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4 files changed

+128
-21
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4 files changed

+128
-21
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‎hdl/xc2c-model/XC2CBitstream.v

+40-14
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,8 @@ module XC2CBitstream(
2727
config_write_en, config_write_addr, config_write_data,
2828
left_zia_config, right_zia_config,
2929
left_and_config, right_and_config,
30-
left_or_config, right_or_config
30+
left_or_config, right_or_config,
31+
left_mc_config, right_mc_config
3132
);
3233

3334
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -58,6 +59,9 @@ module XC2CBitstream(
5859
output reg[16*56-1:0] left_or_config;
5960
output reg[16*56-1:0] right_or_config;
6061

62+
output reg[27*16-1:0] left_mc_config;
63+
output reg[27*16-1:0] right_mc_config;
64+
6165
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
6266
// The SRAM copy of the config bitstream (directly drives device behavior)
6367

@@ -114,11 +118,17 @@ module XC2CBitstream(
114118
integer nbit;
115119
integer nterm;
116120
integer toprow;
121+
integer orow;
122+
integer mcell;
123+
integer mcblock;
117124

118125
always @(*) begin
119126
for(row=0; row<48; row=row+1) begin
120127

121128
toprow = row - 8;
129+
orow = row - 20;
130+
mcell = row / 3;
131+
mcblock = row % 3;
122132

123133
//Rows 0..19: MC-AND-ZIA-AND-MC
124134
//Rows 20...27: MC-OR--GLB-OR--MC
@@ -129,14 +139,14 @@ module XC2CBitstream(
129139
//We have stuff at the top and bottom of array, with global config in the middle
130140
if(row > 27) begin
131141
for(nbit=0; nbit<8; nbit=nbit+1) begin
132-
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][123 + nbit*2];
133-
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][122 + nbit*2];
142+
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][123 + nbit*2];
143+
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][122 + nbit*2];
134144
end
135145
end
136146
else if(row < 20) begin
137147
for(nbit=0; nbit<8; nbit=nbit+1) begin
138-
right_zia_config[row*8 + nbit] <= ram_bitstream[row][123 + nbit*2];
139-
left_zia_config[row*8 + nbit] <= ram_bitstream[row][122 + nbit*2];
148+
right_zia_config[row*8 + nbit] <= ram_bitstream[row][123 + nbit*2];
149+
left_zia_config[row*8 + nbit] <= ram_bitstream[row][122 + nbit*2];
140150
end
141151
end
142152

@@ -146,27 +156,43 @@ module XC2CBitstream(
146156
//Left side: 121:10
147157
if(row > 27) begin
148158
for(nterm=0; nterm<56; nterm=nterm+1) begin
149-
right_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][249 - nterm*2 - 1];
150-
right_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][249 - nterm*2 - 0];
159+
right_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][249 - nterm*2 - 1];
160+
right_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][249 - nterm*2 - 0];
151161

152-
left_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][10 + nterm*2 + 0];
153-
left_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][10 + nterm*2 + 1];
162+
left_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][10 + nterm*2 + 0];
163+
left_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][10 + nterm*2 + 1];
154164
end
155165
end
156166

157167
else if(row < 20) begin
158168
for(nterm=0; nterm<56; nterm=nterm+1) begin
159-
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
160-
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];
169+
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
170+
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];
161171

162-
left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
163-
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
172+
left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
173+
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
164174
end
165175
end
166176

167177
//PLA OR array
178+
//One bit per product term, two OR terms per row
168179
if( (row >= 20) && (row <= 27) ) begin
169-
//TODO
180+
for(nterm=0; nterm<56; nterm=nterm+1) begin
181+
right_or_config[(orow*2)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 0];
182+
right_or_config[(orow*2+1)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 1];
183+
184+
left_or_config[(orow*2)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 0];
185+
left_or_config[(orow*2+1)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 1];
186+
end
187+
end
188+
189+
//Macrocells
190+
//9 bits per row, takes 3 rows to provision one macrocell
191+
//Right side: 258:250 (mirrored)
192+
//Left side: 9:1
193+
for(nbit=0; nbit<9; nbit=nbit+1) begin
194+
left_mc_config[mcell*27 + (2 - mcblock)*9 + nbit] <= ram_bitstream[row][9 - nbit];
195+
right_mc_config[mcell*27 + (2 - mcblock)*9 + nbit] <= ram_bitstream[row][250 + nbit];
170196
end
171197

172198
end

‎hdl/xc2c-model/XC2CDevice.v

+41-6
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,9 @@ module XC2CDevice(
136136
wire[16*56-1:0] left_or_config;
137137
wire[16*56-1:0] right_or_config;
138138

139+
wire[27*16-1:0] left_mc_config;
140+
wire[27*16-1:0] right_mc_config;
141+
139142
XC2CBitstream #(
140143
.ADDR_BITS(ADDR_BITS),
141144
.MEM_DEPTH(MEM_DEPTH),
@@ -156,9 +159,11 @@ module XC2CDevice(
156159
.left_zia_config(left_zia_config),
157160
.left_and_config(left_and_config),
158161
.left_or_config(left_or_config),
162+
.left_mc_config(left_mc_config),
159163
.right_zia_config(right_zia_config),
160164
.right_and_config(right_and_config),
161-
.right_or_config(right_or_config)
165+
.right_or_config(right_or_config),
166+
.right_mc_config(right_mc_config)
162167
);
163168

164169
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -257,6 +262,37 @@ module XC2CDevice(
257262
.or_out(right_orterms)
258263
);
259264

265+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
266+
// Macrocells
267+
268+
wire[15:0] left_mc_out;
269+
wire[15:0] right_mc_out;
270+
271+
genvar g;
272+
generate
273+
for(g=0; g<16; g=g+1) begin : mcells
274+
275+
XC2CMacrocell left(
276+
.config_bits(left_mc_config[g*27 +: 27]),
277+
.pterm_a(left_pterms[g*3 + 8]),
278+
.pterm_b(left_pterms[g*3 + 9]),
279+
.pterm_c(left_pterms[g*3 + 10]),
280+
.or_term(left_orterms[g]),
281+
.mc_out(left_mc_out[g])
282+
);
283+
284+
XC2CMacrocell right(
285+
.config_bits(right_mc_config[g*27 +: 27]),
286+
.pterm_a(right_pterms[g*3 + 8]),
287+
.pterm_b(right_pterms[g*3 + 9]),
288+
.pterm_c(right_pterms[g*3 + 10]),
289+
.or_term(right_orterms[g]),
290+
.mc_out(right_mc_out[g])
291+
);
292+
293+
end
294+
endgenerate
295+
260296
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
261297
// Debug stuff
262298

@@ -268,11 +304,10 @@ module XC2CDevice(
268304
//Drive all unused outputs to 0, then hook up our outputs
269305
//Should be X, !X, X, X
270306
assign iob_out[31:7] = 25'h0;
271-
//assign iob_out[6:3] = {right_pterms[19], right_pterms[22], right_pterms[25], right_pterms[28]};
272-
assign iob_out[6] = ^right_pterms;
273-
assign iob_out[5] = ^left_pterms;
274-
assign iob_out[4] = ^right_orterms;
275-
assign iob_out[3] = ^left_orterms;
307+
assign iob_out[6] = right_mc_out[6];
308+
assign iob_out[5] = right_mc_out[5];
309+
assign iob_out[4] = right_mc_out[4];
310+
assign iob_out[3] = right_mc_out[3];
276311
assign iob_out[2:0] = 3'h0;
277312

278313
endmodule

‎hdl/xc2c-model/XC2CJTAG.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -460,7 +460,7 @@ module XC2CJTAG(
460460
integer i;
461461
initial begin
462462
for(i=0; i<256; i=i+1)
463-
gray_to_bin[i ^ (i >> 1)] <= i;
463+
gray_to_bin[i ^ (i >> 1)] <= i[7:0];
464464
end
465465

466466
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

‎hdl/xc2c-model/XC2CMacrocell.v

+46
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
`default_nettype none
2+
/***********************************************************************************************************************
3+
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
4+
* *
5+
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
6+
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
7+
* any later version. *
8+
* *
9+
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
10+
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
11+
* more details. *
12+
* *
13+
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
14+
* find one here: *
15+
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
16+
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
17+
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
18+
**********************************************************************************************************************/
19+
module XC2CMacrocell(
20+
config_bits,
21+
pterm_a, pterm_b, pterm_c,
22+
or_term,
23+
mc_out
24+
);
25+
26+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
27+
// I/O declarations
28+
29+
input wire[26:0] config_bits;
30+
31+
input wire pterm_a;
32+
input wire pterm_b;
33+
input wire pterm_c;
34+
35+
input wire or_term;
36+
37+
output reg mc_out;
38+
39+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
40+
// XOR logic
41+
42+
always @(*) begin
43+
mc_out <= config_bits == 27'b000001111001111110011111100;
44+
end
45+
46+
endmodule

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