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Initial skeleton of macrocell code. Has correct bitstream values load…
…ed, but largely ignored
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`default_nettype none | ||
/*********************************************************************************************************************** | ||
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors * | ||
* * | ||
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General * | ||
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) * | ||
* any later version. * | ||
* * | ||
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied * | ||
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for * | ||
* more details. * | ||
* * | ||
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may * | ||
* find one here: * | ||
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt * | ||
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software * | ||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA * | ||
**********************************************************************************************************************/ | ||
module XC2CMacrocell( | ||
config_bits, | ||
pterm_a, pterm_b, pterm_c, | ||
or_term, | ||
mc_out | ||
); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// I/O declarations | ||
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input wire[26:0] config_bits; | ||
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input wire pterm_a; | ||
input wire pterm_b; | ||
input wire pterm_c; | ||
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input wire or_term; | ||
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output reg mc_out; | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// XOR logic | ||
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always @(*) begin | ||
mc_out <= config_bits == 27'b000001111001111110011111100; | ||
end | ||
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endmodule |