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Initial skeleton of macrocell code. Has correct bitstream values load…
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…ed, but largely ignored
azonenberg committed Jun 21, 2017
1 parent 73a1180 commit f1282b2
Showing 4 changed files with 128 additions and 21 deletions.
54 changes: 40 additions & 14 deletions hdl/xc2c-model/XC2CBitstream.v
Original file line number Diff line number Diff line change
@@ -27,7 +27,8 @@ module XC2CBitstream(
config_write_en, config_write_addr, config_write_data,
left_zia_config, right_zia_config,
left_and_config, right_and_config,
left_or_config, right_or_config
left_or_config, right_or_config,
left_mc_config, right_mc_config
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -58,6 +59,9 @@ module XC2CBitstream(
output reg[16*56-1:0] left_or_config;
output reg[16*56-1:0] right_or_config;

output reg[27*16-1:0] left_mc_config;
output reg[27*16-1:0] right_mc_config;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The SRAM copy of the config bitstream (directly drives device behavior)

@@ -114,11 +118,17 @@ module XC2CBitstream(
integer nbit;
integer nterm;
integer toprow;
integer orow;
integer mcell;
integer mcblock;

always @(*) begin
for(row=0; row<48; row=row+1) begin

toprow = row - 8;
orow = row - 20;
mcell = row / 3;
mcblock = row % 3;

//Rows 0..19: MC-AND-ZIA-AND-MC
//Rows 20...27: MC-OR--GLB-OR--MC
@@ -129,14 +139,14 @@ module XC2CBitstream(
//We have stuff at the top and bottom of array, with global config in the middle
if(row > 27) begin
for(nbit=0; nbit<8; nbit=nbit+1) begin
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][123 + nbit*2];
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][122 + nbit*2];
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][123 + nbit*2];
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][122 + nbit*2];
end
end
else if(row < 20) begin
for(nbit=0; nbit<8; nbit=nbit+1) begin
right_zia_config[row*8 + nbit] <= ram_bitstream[row][123 + nbit*2];
left_zia_config[row*8 + nbit] <= ram_bitstream[row][122 + nbit*2];
right_zia_config[row*8 + nbit] <= ram_bitstream[row][123 + nbit*2];
left_zia_config[row*8 + nbit] <= ram_bitstream[row][122 + nbit*2];
end
end

@@ -146,27 +156,43 @@ module XC2CBitstream(
//Left side: 121:10
if(row > 27) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][249 - nterm*2 - 1];
right_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][249 - nterm*2 - 0];
right_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][249 - nterm*2 - 1];
right_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][249 - nterm*2 - 0];

left_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][10 + nterm*2 + 0];
left_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][10 + nterm*2 + 1];
left_and_config[nterm*80 + toprow*2 + 0] <= ram_bitstream[toprow][10 + nterm*2 + 0];
left_and_config[nterm*80 + toprow*2 + 1] <= ram_bitstream[toprow][10 + nterm*2 + 1];
end
end

else if(row < 20) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];
right_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][249 - nterm*2 - 1];
right_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][249 - nterm*2 - 0];

left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
left_and_config[nterm*80 + row*2 + 0] <= ram_bitstream[row][10 + nterm*2 + 0];
left_and_config[nterm*80 + row*2 + 1] <= ram_bitstream[row][10 + nterm*2 + 1];
end
end

//PLA OR array
//One bit per product term, two OR terms per row
if( (row >= 20) && (row <= 27) ) begin
//TODO
for(nterm=0; nterm<56; nterm=nterm+1) begin
right_or_config[(orow*2)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 0];
right_or_config[(orow*2+1)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 1];

left_or_config[(orow*2)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 0];
left_or_config[(orow*2+1)*56 + nterm] <= ram_bitstream[orow][249 - nterm*2 + 1];
end
end

//Macrocells
//9 bits per row, takes 3 rows to provision one macrocell
//Right side: 258:250 (mirrored)
//Left side: 9:1
for(nbit=0; nbit<9; nbit=nbit+1) begin
left_mc_config[mcell*27 + (2 - mcblock)*9 + nbit] <= ram_bitstream[row][9 - nbit];
right_mc_config[mcell*27 + (2 - mcblock)*9 + nbit] <= ram_bitstream[row][250 + nbit];
end

end
47 changes: 41 additions & 6 deletions hdl/xc2c-model/XC2CDevice.v
Original file line number Diff line number Diff line change
@@ -136,6 +136,9 @@ module XC2CDevice(
wire[16*56-1:0] left_or_config;
wire[16*56-1:0] right_or_config;

wire[27*16-1:0] left_mc_config;
wire[27*16-1:0] right_mc_config;

XC2CBitstream #(
.ADDR_BITS(ADDR_BITS),
.MEM_DEPTH(MEM_DEPTH),
@@ -156,9 +159,11 @@ module XC2CDevice(
.left_zia_config(left_zia_config),
.left_and_config(left_and_config),
.left_or_config(left_or_config),
.left_mc_config(left_mc_config),
.right_zia_config(right_zia_config),
.right_and_config(right_and_config),
.right_or_config(right_or_config)
.right_or_config(right_or_config),
.right_mc_config(right_mc_config)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -257,6 +262,37 @@ module XC2CDevice(
.or_out(right_orterms)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Macrocells

wire[15:0] left_mc_out;
wire[15:0] right_mc_out;

genvar g;
generate
for(g=0; g<16; g=g+1) begin : mcells

XC2CMacrocell left(
.config_bits(left_mc_config[g*27 +: 27]),
.pterm_a(left_pterms[g*3 + 8]),
.pterm_b(left_pterms[g*3 + 9]),
.pterm_c(left_pterms[g*3 + 10]),
.or_term(left_orterms[g]),
.mc_out(left_mc_out[g])
);

XC2CMacrocell right(
.config_bits(right_mc_config[g*27 +: 27]),
.pterm_a(right_pterms[g*3 + 8]),
.pterm_b(right_pterms[g*3 + 9]),
.pterm_c(right_pterms[g*3 + 10]),
.or_term(right_orterms[g]),
.mc_out(right_mc_out[g])
);

end
endgenerate

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Debug stuff

@@ -268,11 +304,10 @@ module XC2CDevice(
//Drive all unused outputs to 0, then hook up our outputs
//Should be X, !X, X, X
assign iob_out[31:7] = 25'h0;
//assign iob_out[6:3] = {right_pterms[19], right_pterms[22], right_pterms[25], right_pterms[28]};
assign iob_out[6] = ^right_pterms;
assign iob_out[5] = ^left_pterms;
assign iob_out[4] = ^right_orterms;
assign iob_out[3] = ^left_orterms;
assign iob_out[6] = right_mc_out[6];
assign iob_out[5] = right_mc_out[5];
assign iob_out[4] = right_mc_out[4];
assign iob_out[3] = right_mc_out[3];
assign iob_out[2:0] = 3'h0;

endmodule
2 changes: 1 addition & 1 deletion hdl/xc2c-model/XC2CJTAG.v
Original file line number Diff line number Diff line change
@@ -460,7 +460,7 @@ module XC2CJTAG(
integer i;
initial begin
for(i=0; i<256; i=i+1)
gray_to_bin[i ^ (i >> 1)] <= i;
gray_to_bin[i ^ (i >> 1)] <= i[7:0];
end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
46 changes: 46 additions & 0 deletions hdl/xc2c-model/XC2CMacrocell.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
`default_nettype none
/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
module XC2CMacrocell(
config_bits,
pterm_a, pterm_b, pterm_c,
or_term,
mc_out
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations

input wire[26:0] config_bits;

input wire pterm_a;
input wire pterm_b;
input wire pterm_c;

input wire or_term;

output reg mc_out;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// XOR logic

always @(*) begin
mc_out <= config_bits == 27'b000001111001111110011111100;
end

endmodule

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