Continued initial macrocell implementation. Fixed bugs in AND array inversion. Now can do arbitrary Boolean combinatorial logic from ZIA to macrocell XOR gate, but no feedback to ZIA or stateful stuff implemented.

azonenberg · azonenberg · commit 1f7d800dbd08 · 2017-06-20T23:56:10.000-07:00
diff --git a/hdl/xc2c-model/XC2CAndArray.v b/hdl/xc2c-model/XC2CAndArray.v
@@ -55,9 +55,9 @@ module XC2CAndArray(zia_in, config_bits, pterm_out);
 			//AND in the ZIA stuff
 			for(nrow=0; nrow<40; nrow=nrow+1) begin
 				if(!and_config[nterm][nrow*2])
-					pterm_out[nterm] = pterm_out[nterm] & zia_in[nrow];
+					pterm_out[nterm] = pterm_out[nterm] & ~zia_in[nrow];
 				if(!and_config[nterm][nrow*2 + 1])
-					pterm_out[nterm] = pterm_out[nterm] & !zia_in[nrow];
+					pterm_out[nterm] = pterm_out[nterm] & zia_in[nrow];
 			end
 		end
 	end
diff --git a/hdl/xc2c-model/XC2CBitstream.v b/hdl/xc2c-model/XC2CBitstream.v
@@ -178,11 +178,11 @@ module XC2CBitstream(
 			//One bit per product term, two OR terms per row
 			if( (row >= 20) && (row <= 27) ) begin
 				for(nterm=0; nterm<56; nterm=nterm+1) begin
-					right_or_config[(orow*2)*56 + nterm]		<= ram_bitstream[orow][249 - nterm*2 + 0];
-					right_or_config[(orow*2+1)*56 + nterm]		<= ram_bitstream[orow][249 - nterm*2 + 1];
+					right_or_config[(orow*2)*56 + nterm]		<= ram_bitstream[orow][249 - nterm*2 - 0];
+					right_or_config[(orow*2+1)*56 + nterm]		<= ram_bitstream[orow][249 - nterm*2 - 1];
 
-					left_or_config[(orow*2)*56 + nterm]			<= ram_bitstream[orow][249 - nterm*2 + 0];
-					left_or_config[(orow*2+1)*56 + nterm]		<= ram_bitstream[orow][249 - nterm*2 + 1];
+					left_or_config[(orow*2)*56 + nterm]			<= ram_bitstream[orow][10 + nterm*2 + 0];
+					left_or_config[(orow*2+1)*56 + nterm]		<= ram_bitstream[orow][10 + nterm*2 + 1];
 				end
 			end
 
diff --git a/hdl/xc2c-model/XC2CDevice.v b/hdl/xc2c-model/XC2CDevice.v
@@ -22,7 +22,9 @@
  */
 module XC2CDevice(
 	jtag_tdi, jtag_tms, jtag_tck, jtag_tdo,
-	dedicated_input, iob_out, iob_in, iob_t);
+	dedicated_input, iob_out, iob_in, iob_t,
+	done, dbgout
+	);
 
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 	// Device configuration
@@ -114,6 +116,9 @@ module XC2CDevice(
 	output wire[MACROCELLS-1:0]	iob_t;
 	input wire[MACROCELLS-1:0]	iob_in;
 
+	output wire					done;
+	output wire					dbgout;
+
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 	// The bitstream
 
@@ -188,7 +193,9 @@ module XC2CDevice(
 
 		.config_write_en(config_write_en),
 		.config_write_addr(config_write_addr),
-		.config_write_data(config_write_data)
+		.config_write_data(config_write_data),
+
+		.config_done(done)
 	);
 
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -308,6 +315,14 @@ module XC2CDevice(
 	assign iob_out[5] = right_mc_out[5];
 	assign iob_out[4] = right_mc_out[4];
 	assign iob_out[3] = right_mc_out[3];
+
+	//assign iob_out[5] = right_pterms[22];		//pterm, should be copy of x
+	//assign iob_out[4] = right_mc_out[3];		//led_0, constant 1: OR arrays 0 xor 1
+	//assign iob_out[3] = right_mc_out[4];		//led_1, passthrough of pterm C
+												//for MC4 this is pterm 22
 	assign iob_out[2:0] = 3'h0;
 
+	//Helper to keep stuff from getting optimized out
+	assign dbgout = ^right_mc_out ^ ^left_mc_out;
+
 endmodule
diff --git a/hdl/xc2c-model/XC2CJTAG.v b/hdl/xc2c-model/XC2CJTAG.v
@@ -24,7 +24,8 @@ module XC2CJTAG(
 	tdi, tms, tck, tdo,
 	config_erase,
 	config_read_en, config_read_addr, config_read_data,
-	config_write_en, config_write_addr, config_write_data);
+	config_write_en, config_write_addr, config_write_data,
+	config_done);
 
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 	// Device configuration
@@ -57,6 +58,8 @@ module XC2CJTAG(
 	output reg[ADDR_BITS-1:0]	config_write_addr	= 0;
 	output reg[SHREG_WIDTH-1:0]	config_write_data	= 0;
 
+	output wire					config_done;
+
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 	// The core JTAG state machine
 
@@ -195,6 +198,8 @@ module XC2CJTAG(
 	reg			configured				= 0;
 	reg			read_locked				= 0;
 
+	assign		config_done = configured;
+
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 	// The instruction register
 
diff --git a/hdl/xc2c-model/XC2CMacrocell.v b/hdl/xc2c-model/XC2CMacrocell.v
@@ -37,10 +37,25 @@ module XC2CMacrocell(
 	output reg					mc_out;
 
 	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-	// XOR logic
+	// Macrocell XOR
+
+	reg							xor_out;
+
+	always @(*) begin
+
+		case(config_bits[9:8])
+			2'h0:	xor_out		<= or_term ^ 1'b0;
+			2'h1:	xor_out		<= or_term ^ ~pterm_c;
+			2'h2:	xor_out		<= or_term ^ pterm_c;
+			2'h3:	xor_out		<= or_term ^ 1'b1;
+		endcase
+	end
+
+	////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+	// Final output muxing
 
 	always @(*) begin
-		mc_out					<= config_bits == 27'b000001111001111110011111100;
+		mc_out					<= xor_out;
 	end
 
 endmodule
