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base repository: azonenberg/yosys
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  • 5 commits
  • 5 files changed
  • 1 contributor

Commits on Jun 27, 2017

  1. Merge pull request YosysHQ#353 from azonenberg/master

    greenpak4_counters: Use more human-readable names for inferred counters
    cliffordwolf authored Jun 27, 2017
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    5b95901 View commit details

Commits on Jun 30, 2017

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    18c030a View commit details
  2. Add chtype command

    cliffordwolf committed Jun 30, 2017
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    8952bd6 View commit details
  3. Add "design -import"

    cliffordwolf committed Jun 30, 2017
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Commits on Jul 1, 2017

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Showing with 182 additions and 6 deletions.
  1. +3 −3 backends/smt2/smtbmc.py
  2. +1 −0 passes/cmds/Makefile.inc
  3. +83 −0 passes/cmds/chtype.cc
  4. +94 −3 passes/cmds/design.cc
  5. +1 −0 passes/opt/opt_merge.cc
6 changes: 3 additions & 3 deletions backends/smt2/smtbmc.py
Original file line number Diff line number Diff line change
@@ -755,11 +755,11 @@ def write_vlogtb_trace(steps_start, steps_stop, index):

for info in anyseqs:
if info[3] is not None:
modstate = smt.net_expr(topmod, "s%d" % steps_start, info[0])
modstate = smt.net_expr(topmod, "s%d" % i, info[0])
value = smt.bv2bin(smt.get("(|%s| %s)" % (info[1], modstate)))
print(" UUT.%s = %d'b%s;" % (".".join(info[0] + [info[3]]), len(value), value), file=f);
print(" UUT.%s <= %d'b%s;" % (".".join(info[0] + [info[3]]), len(value), value), file=f);

print(" genclock = 0;", file=f)
print(" genclock <= 0;", file=f)
print(" end", file=f)

print("endmodule", file=f)
1 change: 1 addition & 0 deletions passes/cmds/Makefile.inc
Original file line number Diff line number Diff line change
@@ -26,4 +26,5 @@ OBJS += passes/cmds/check.o
OBJS += passes/cmds/qwp.o
OBJS += passes/cmds/edgetypes.o
OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o

83 changes: 83 additions & 0 deletions passes/cmds/chtype.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,83 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/

#include "kernel/yosys.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct ChtypePass : public Pass {
ChtypePass() : Pass("chtype", "change type of cells in the design") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" chtype [options] [selection]\n");
log("\n");
log("Change the types of cells in the design.\n");
log("\n");
log(" -set <type>\n");
log(" set the cell type to the given type\n");
log("\n");
log(" -map <old_type> <new_type>\n");
log(" change cells types that match <old_type> to <new_type>\n");
log("\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
IdString set_type;
dict<IdString, IdString> map_types;

size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (set_type == IdString() && args[argidx] == "-set" && argidx+1 < args.size()) {
set_type = RTLIL::escape_id(args[++argidx]);
continue;
}
if (args[argidx] == "-map" && argidx+2 < args.size()) {
IdString old_type = RTLIL::escape_id(args[++argidx]);
IdString new_type = RTLIL::escape_id(args[++argidx]);
map_types[old_type] = new_type;
continue;
}
break;
}
extra_args(args, argidx, design);

for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
{
if (map_types.count(cell->type)) {
cell->type = map_types.at(cell->type);
continue;
}

if (set_type != IdString()) {
cell->type = set_type;
continue;
}
}
}
}
} ChtypePass;

PRIVATE_NAMESPACE_END
97 changes: 94 additions & 3 deletions passes/cmds/design.cc
Original file line number Diff line number Diff line change
@@ -81,6 +81,13 @@ struct DesignPass : public Pass {
log("Copy modules from the current design into the specified one.\n");
log("\n");
log("\n");
log(" design -import <name> [-as <new_top_name>] [selection]\n");
log("\n");
log("Import the specified design into the current design. The source design must\n");
log("either have a selected top module or the selection must contain exactly one\n");
log("module that is then used as top module for this command.\n");
log("\n");
log("\n");
log(" design -reset-vlog\n");
log("\n");
log("The Verilog front-end remembers defined macros and top-level declarations\n");
@@ -94,6 +101,7 @@ struct DesignPass : public Pass {
bool reset_vlog_mode = false;
bool push_mode = false;
bool pop_mode = false;
bool import_mode = false;
RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
std::string save_name, load_name, as_name;
std::vector<RTLIL::Module*> copy_src_modules;
@@ -156,8 +164,17 @@ struct DesignPass : public Pass {
copy_from_design = design;
continue;
}
if (copy_from_design != NULL && args[argidx] == "-as" && argidx+1 < args.size()) {
if (!got_mode && args[argidx] == "-import" && argidx+1 < args.size()) {
got_mode = true;
import_mode = true;
if (saved_designs.count(args[++argidx]) == 0)
log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
copy_from_design = saved_designs.at(args[argidx]);
copy_to_design = design;
as_name = args[argidx];
continue;
}
if (copy_from_design != NULL && args[argidx] == "-as" && argidx+1 < args.size()) {
as_name = args[++argidx];
continue;
}
@@ -166,10 +183,10 @@ struct DesignPass : public Pass {

if (copy_from_design != NULL)
{
if (copy_from_design != design && argidx == args.size())
if (copy_from_design != design && argidx == args.size() && !import_mode)
cmd_error(args, argidx, "Missing selection.");

RTLIL::Selection sel = design->selection_stack.back();
RTLIL::Selection sel;
if (argidx != args.size()) {
handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
sel = copy_from_design->selection_stack.back();
@@ -185,6 +202,17 @@ struct DesignPass : public Pass {
if (sel.selected_module(it.first))
log_cmd_error("Module %s is only partly selected.\n", RTLIL::id2cstr(it.first));
}

if (import_mode) {
for (auto module : copy_src_modules)
{
if (module->get_bool_attribute("\\top")) {
copy_src_modules.clear();
copy_src_modules.push_back(module);
break;
}
}
}
}

extra_args(args, argidx, design, false);
@@ -195,6 +223,68 @@ struct DesignPass : public Pass {
if (pop_mode && pushed_designs.empty())
log_cmd_error("No pushed designs.\n");

if (import_mode)
{
std::string prefix = RTLIL::escape_id(as_name);

pool<Module*> queue;
dict<IdString, IdString> done;

if (copy_to_design->modules_.count(prefix))
delete copy_to_design->modules_.at(prefix);

if (GetSize(copy_src_modules) != 1)
log_cmd_error("No top module found in source design.\n");

for (auto mod : copy_src_modules)
{
log("Importing %s as %s.\n", log_id(mod), log_id(prefix));

copy_to_design->modules_[prefix] = mod->clone();
copy_to_design->modules_[prefix]->name = prefix;
copy_to_design->modules_[prefix]->design = copy_to_design;
copy_to_design->modules_[prefix]->attributes.erase("\\top");

queue.insert(copy_to_design->modules_[prefix]);
done[mod->name] = prefix;
}

while (!queue.empty())
{
pool<Module*> old_queue;
old_queue.swap(queue);

for (auto mod : old_queue)
for (auto cell : mod->cells())
{
Module *fmod = copy_from_design->module(cell->type);

if (fmod == nullptr)
continue;

if (done.count(cell->type) == 0)
{
std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\'));

log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));

if (copy_to_design->modules_.count(trg_name))
delete copy_to_design->modules_.at(trg_name);

copy_to_design->modules_[trg_name] = fmod->clone();
copy_to_design->modules_[trg_name]->name = trg_name;
copy_to_design->modules_[trg_name]->design = copy_to_design;
copy_to_design->modules_[trg_name]->attributes.erase("\\top");

queue.insert(copy_to_design->modules_[trg_name]);
done[cell->type] = trg_name;
}

cell->type = done.at(cell->type);
}
}
}
else
if (copy_to_design != NULL)
{
if (!as_name.empty() && copy_src_modules.size() > 1)
@@ -206,6 +296,7 @@ struct DesignPass : public Pass {

if (copy_to_design->modules_.count(trg_name))
delete copy_to_design->modules_.at(trg_name);

copy_to_design->modules_[trg_name] = mod->clone();
copy_to_design->modules_[trg_name]->name = trg_name;
copy_to_design->modules_[trg_name]->design = copy_to_design;
1 change: 1 addition & 0 deletions passes/opt/opt_merge.cc
Original file line number Diff line number Diff line change
@@ -275,6 +275,7 @@ struct OptMergeWorker
ct.cell_types.erase("$pmux");
}

ct.cell_types.erase("$tribuf");
ct.cell_types.erase("$anyseq");
ct.cell_types.erase("$anyconst");