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committedJul 7, 2017
Updated README, reviving this project
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‎LICENSE

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Copyright (c) 2015, Andrew Zonenberg
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Copyright (c) 2015-2017, Andrew Zonenberg
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All rights reserved.
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Redistribution and use in source and binary forms, with or without

‎README.md

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# netlist-tools
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Automated analysis tools for turning reverse-engineered IC bitmaps (from a machine vision tool) into transistor-level (and eventually gate level) netlists. Very early prototype as well as my first Python3 project, do not expect this to work!
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Automated analysis tools for turning gate-level netlists from FPGA bitstreams, machine vision tools, etc into
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high-level RTL netlists.

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