-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Updated README, reviving this project
1 parent
0f7c381
commit f180e0d
Showing
2 changed files
with
3 additions
and
2 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,2 +1,3 @@ | ||
# netlist-tools | ||
Automated analysis tools for turning reverse-engineered IC bitmaps (from a machine vision tool) into transistor-level (and eventually gate level) netlists. Very early prototype as well as my first Python3 project, do not expect this to work! | ||
Automated analysis tools for turning gate-level netlists from FPGA bitstreams, machine vision tools, etc into | ||
high-level RTL netlists. |