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cordic: make interior registers reset_less
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* the understanding is that the CORDIC does not hold a state that should
or could be reset. the internal registers are all fully defined by the
inputs and will be reset (with the pipeline delay) by resetting the
inputs.
* the stage counter in the iterative implementation retains its reset

* significantly reduces reset congestion due to reset net in big designs
jordens committed Jun 28, 2017
1 parent 58666ae commit 1d3fbc4
Showing 1 changed file with 8 additions and 5 deletions.
13 changes: 8 additions & 5 deletions misoc/cores/cordic.py
Original file line number Diff line number Diff line change
@@ -209,9 +209,12 @@ def __init__(self, width=16, widthz=None, stages=None, guard=0,
self.latency = 0

# inter-stage signals
x = [Signal((width + guard, True)) for i in range(num_sig)]
y = [Signal((width + guard, True)) for i in range(num_sig)]
z = [Signal((widthz + guard, True)) for i in range(num_sig)]
x = [Signal((width + guard, True), reset_less=True)
for i in range(num_sig)]
y = [Signal((width + guard, True), reset_less=True)
for i in range(num_sig)]
z = [Signal((widthz + guard, True), reset_less=True)
for i in range(num_sig)]

# hook up inputs and outputs to the first and last inter-stage
# signals
@@ -231,12 +234,12 @@ def __init__(self, width=16, widthz=None, stages=None, guard=0,
self.new_in.eq(i == stages),
self.new_out.eq(i == 1),
]
ai = Signal((widthz + guard, True))
ai = Signal((widthz + guard, True), reset_less=True)
self.sync += ai.eq(Array(a)[i])
if range(stages) == s:
si = i - 1 # shortcut if no stage repetitions
else:
si = Signal(max=stages + 1)
si = Signal(max=stages + 1, reset_less=True)
self.sync += si.eq(Array(s)[i])
xi, yi, zi = x[1], y[1], z[1]
self.sync += [

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