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vivado: mark ars_ff1 and ars_ff2 explicitly
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avoid the 2 ns delay rule erroneously catching any paths between
two reset synchronizers (ff2 -> ff1).
jordens committed Jun 30, 2017
1 parent e4ae7b3 commit e2b5d6f
Showing 3 changed files with 13 additions and 10 deletions.
4 changes: 2 additions & 2 deletions migen/build/xilinx/common.py
Original file line number Diff line number Diff line change
@@ -83,10 +83,10 @@ def __init__(self, cd, async_reset):
self.specials += [
Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
i_CE=1, i_C=cd.clk, o_Q=rst_meta,
attr={"async_reg", "ars_ff"}),
attr={"async_reg", "ars_ff1"}),
Instance("FDPE", p_INIT=1, i_D=rst_meta, i_PRE=async_reset,
i_CE=1, i_C=cd.clk, o_Q=cd.rst,
attr={"async_reg", "ars_ff"})
attr={"async_reg", "ars_ff2"})
]
async_reset.attr.add("ars_false_path")

3 changes: 2 additions & 1 deletion migen/build/xilinx/ise.py
Original file line number Diff line number Diff line change
@@ -129,7 +129,8 @@ class XilinxISEToolchain:
"keep": ("keep", "true"),
"no_retiming": ("register_balancing", "no"),
"async_reg": None,
"ars_ff": None,
"ars_ff1": None,
"ars_ff2": None,
"ars_false_path": None,
"no_shreg_extract": ("shreg_extract", "no")
}
16 changes: 9 additions & 7 deletions migen/build/xilinx/vivado.py
Original file line number Diff line number Diff line change
@@ -75,7 +75,8 @@ class XilinxVivadoToolchain:
"keep": ("dont_touch", "true"),
"no_retiming": ("dont_touch", "true"),
"async_reg": ("async_reg", "true"),
"ars_ff": ("ars_ff", "true"), # user-defined attribute
"ars_ff1": ("ars_ff1", "true"), # user-defined attribute
"ars_ff2": ("ars_ff2", "true"), # user-defined attribute
"ars_false_path": ("ars_false_path", "true"), # user-defined attribute
"no_shreg_extract": None
}
@@ -90,8 +91,9 @@ def __init__(self):

def _build_batch(self, platform, sources, build_name):
tcl = []
tcl.append("create_property ars_ff cell")
tcl.append("create_property ars_false_path net")
tcl.append("create_property -type bool ars_ff1 cell")
tcl.append("create_property -type bool ars_ff2 cell")
tcl.append("create_property -type bool ars_false_path net")
for filename, language, library in sources:
filename_tcl = "{" + filename + "}"
tcl.append("add_files " + filename_tcl)
@@ -157,15 +159,15 @@ def _constrain(self, platform):
# path
platform.add_platform_command(
"set_false_path -quiet "
"-through [get_nets -hier -filter {{ars_false_path==true}}] "
"-to [get_cells -hier -filter {{ars_ff==true}}]"
"-through [get_nets -hier -filter ars_false_path] "
"-to [get_cells -hier -filter {{ars_ff1 || ars_ff2}}]"
)
# clock_period-2ns to resolve metastability on the wire between the
# AsyncResetSynchronizer FFs
platform.add_platform_command(
"set_max_delay 2 -quiet "
"-from [get_cells -hier -filter {{ars_ff==true}}] "
"-to [get_cells -hier -filter {{ars_ff==true}}]"
"-from [get_cells -hier -filter ars_ff1] "
"-to [get_cells -hier -filter ars_ff2]"
)

def build(self, platform, fragment, build_dir="build", build_name="top",

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