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base repository: azonenberg/openfpga
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Jun 26, 2017

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Showing with 203 additions and 15 deletions.
  1. +4 −4 hdl/xc2c-model/XC2CBitstream.v
  2. +28 −4 hdl/xc2c-model/XC2CDevice.v
  3. +171 −7 hdl/xc2c-model/XC2CMacrocell.v
8 changes: 4 additions & 4 deletions hdl/xc2c-model/XC2CBitstream.v
Original file line number Diff line number Diff line change
@@ -164,14 +164,14 @@ module XC2CBitstream(
//We have stuff at the top and bottom of array, with global config in the middle
if(row > 27) begin
for(nbit=0; nbit<8; nbit=nbit+1) begin
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][123 + nbit*2];
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][122 + nbit*2];
right_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][137 - nbit*2];
left_zia_config[toprow*8 + nbit] <= ram_bitstream[toprow][136 - nbit*2];
end
end
else if(row < 20) begin
for(nbit=0; nbit<8; nbit=nbit+1) begin
right_zia_config[row*8 + nbit] <= ram_bitstream[row][123 + nbit*2];
left_zia_config[row*8 + nbit] <= ram_bitstream[row][122 + nbit*2];
right_zia_config[row*8 + nbit] <= ram_bitstream[row][137 - nbit*2];
left_zia_config[row*8 + nbit] <= ram_bitstream[row][136 - nbit*2];
end
end

32 changes: 28 additions & 4 deletions hdl/xc2c-model/XC2CDevice.v
Original file line number Diff line number Diff line change
@@ -176,6 +176,9 @@ module XC2CDevice(

wire config_done_rst;

wire config_erase_raw;
BUFG bufg_reset(.I(config_erase_raw), .O(config_erase));

XC2CJTAG #(
.MACROCELLS(MACROCELLS),
.PACKAGE(PACKAGE),
@@ -187,7 +190,7 @@ module XC2CDevice(
.tms(jtag_tms),
.tck(jtag_tck),

.config_erase(config_erase),
.config_erase(config_erase_raw),

.config_read_en(config_read_en),
.config_read_addr(config_read_addr),
@@ -272,12 +275,28 @@ module XC2CDevice(
.or_out(right_orterms)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Global clock buffers

//TODO: gclk enables
wire[2:0] global_ce = 3'b111;

wire[2:0] global_clk;
BUFGCE bufg_gclk0(.I(iob_in[20]), .O(global_clk[0]), .CE(global_ce[0]));
BUFGCE bufg_gclk1(.I(iob_in[21]), .O(global_clk[1]), .CE(global_ce[1]));
BUFGCE bufg_gclk2(.I(iob_in[22]), .O(global_clk[2]), .CE(global_ce[2]));

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Macrocells

wire[15:0] left_mc_to_obuf;
wire[15:0] right_mc_to_obuf;

wire left_cterm_clk;
wire right_cterm_clk;
BUFG bufg_left_ctc(.I(left_pterms[4]), .O(left_cterm_clk));
BUFG bufg_right_ctc(.I(right_pterms[4]), .O(right_cterm_clk));

genvar g;
generate
for(g=0; g<16; g=g+1) begin : mcells
@@ -288,9 +307,12 @@ module XC2CDevice(
.pterm_b(left_pterms[g*3 + 9]),
.pterm_c(left_pterms[g*3 + 10]),
.or_term(left_orterms[g]),
.cterm_clk(left_cterm_clk),
.global_clk(global_clk),
.config_done_rst(config_done_rst),
.mc_to_zia(macrocell_to_zia[g + 16]),
.mc_to_obuf(left_mc_to_obuf[g])
.mc_to_obuf(left_mc_to_obuf[g]),
.raw_ibuf(iob_in[g + 16])
);

XC2CMacrocell right(
@@ -299,9 +321,12 @@ module XC2CDevice(
.pterm_b(right_pterms[g*3 + 9]),
.pterm_c(right_pterms[g*3 + 10]),
.or_term(right_orterms[g]),
.cterm_clk(right_cterm_clk),
.global_clk(global_clk),
.config_done_rst(config_done_rst),
.mc_to_zia(macrocell_to_zia[g]),
.mc_to_obuf(right_mc_to_obuf[g])
.mc_to_obuf(right_mc_to_obuf[g]),
.raw_ibuf(iob_in[g])
);

end
@@ -322,7 +347,6 @@ module XC2CDevice(
assign iob_out[5] = right_mc_to_obuf[5];
assign iob_out[4] = right_mc_to_obuf[4];
assign iob_out[3] = right_mc_to_obuf[3];

assign iob_out[2:0] = 3'h0;

//Helper to keep stuff from getting optimized out
178 changes: 171 additions & 7 deletions hdl/xc2c-model/XC2CMacrocell.v
Original file line number Diff line number Diff line change
@@ -20,7 +20,9 @@ module XC2CMacrocell(
config_bits,
pterm_a, pterm_b, pterm_c,
or_term,
cterm_clk, global_clk,
mc_to_zia, mc_to_obuf,
raw_ibuf,
config_done_rst
);

@@ -34,11 +36,17 @@ module XC2CMacrocell(
input wire pterm_c;

input wire or_term;
input wire config_done_rst;

input wire cterm_clk;
input wire[2:0] global_clk;

output reg mc_to_zia;
output reg mc_to_obuf;

input wire raw_ibuf;

input wire config_done_rst;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Macrocell XOR

@@ -54,14 +62,170 @@ module XC2CMacrocell(
endcase
end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FF input muxing

//TODO: implement latch mode

reg dff_imux;

reg dff_in;
always @(*) begin

//Normal input source mux
if(config_bits[11])
dff_imux <= xor_out;
else
dff_imux <= raw_ibuf;

//T flipflop has inverting feedback path
if(config_bits[17:16] == 2) begin

//Toggling?
if(dff_imux)
dff_in <= ~mc_dff_muxed;

//Nope, preserve it
else
dff_in <= mc_dff_muxed;

end

//D flipflop just takes data from input
else
dff_in <= dff_imux;


end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FF clock enable

reg dff_ce;

always @(*) begin

//We have a clock enable
if(config_bits[17:16] == 3)
dff_ce <= pterm_c;

//No clock enable, always on
else
dff_ce <= 1'b1;

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FF set/reset logic

reg dff_sr;
reg dff_srval;

always @(*) begin

//Power-on reset
if(config_done_rst) begin
dff_sr <= 1;
dff_srval <= !config_bits[0];
end

//TODO: set/reset inputs
else begin
dff_sr <= 0;
dff_srval <= 0;
end

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Macrocell flipflop

reg mc_dff = 1;
wire dff_rising_en = !config_bits[25] || config_bits[22];
wire dff_falling_en = config_bits[25] || config_bits[22];

//FF is replicated a bunch of times b/c of complex clocking structure.
//It's not too practical to have a FF with one of many possible clocks in a 7-series device.
//It's way easier to just have one FF per clock, then mux the outputs combinatorially.

wire mc_dff_ctc;
ConfigurableEdgeFlipflop ff_ctc(
.d(dff_in),
.clk(cterm_clk),
.ce(dff_ce),
.sr(dff_sr),
.srval(dff_srval),
.q(mc_dff_ctc),
.rising_en(dff_rising_en),
.falling_en(dff_falling_en)
);

wire mc_dff_ptc;
ConfigurableEdgeFlipflop ff_ptc(
.d(dff_in),
.clk(pterm_c),
.ce(dff_ce),
.sr(dff_sr),
.srval(dff_srval),
.q(mc_dff_ptc),
.rising_en(dff_rising_en),
.falling_en(dff_falling_en)
);

wire mc_dff_gck0;
ConfigurableEdgeFlipflop ff_gck0(
.d(dff_in),
.clk(global_clk[0]),
.ce(dff_ce),
.sr(dff_sr),
.srval(dff_srval),
.q(mc_dff_gck0),
.rising_en(dff_rising_en),
.falling_en(dff_falling_en)
);

wire mc_dff_gck1;
ConfigurableEdgeFlipflop ff_gck1(
.d(dff_in),
.clk(global_clk[1]),
.ce(dff_ce),
.sr(dff_sr),
.srval(dff_srval),
.q(mc_dff_gck1),
.rising_en(dff_rising_en),
.falling_en(dff_falling_en)
);

wire mc_dff_gck2;
ConfigurableEdgeFlipflop ff_gck2(
.d(dff_in),
.clk(global_clk[2]),
.ce(dff_ce),
.sr(dff_sr),
.srval(dff_srval),
.q(mc_dff_gck2),
.rising_en(dff_rising_en),
.falling_en(dff_falling_en)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FF output muxing

//Final clock output mux
reg mc_dff_muxed;
always @(*) begin

case(config_bits[24:23])
0: mc_dff_muxed <= mc_dff_gck0;
1: mc_dff_muxed <= mc_dff_gck2;
2: mc_dff_muxed <= mc_dff_gck1;
3: begin
if(config_bits[26])
mc_dff_muxed <= mc_dff_ctc;
else
mc_dff_muxed <= mc_dff_ptc;
end
endcase

//Flipflop reset
always @(/*posedge config_done_rst*/*) begin
mc_dff <= !config_bits[0];
end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -76,7 +240,7 @@ module XC2CMacrocell(

//See where macrocell->ZIA driver should go
if(config_bits[13])
mc_to_zia <= mc_dff;
mc_to_zia <= mc_dff_muxed;
else
mc_to_zia <= xor_out;

@@ -90,7 +254,7 @@ module XC2CMacrocell(
if(config_bits[7])
mc_to_obuf <= xor_out;
else
mc_to_obuf <= mc_dff;
mc_to_obuf <= mc_dff_muxed;

end