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  • 2 commits
  • 6 files changed
  • 1 contributor

Commits on Oct 19, 2016

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Showing with 243 additions and 12 deletions.
  1. +74 −5 doc/gp4-hdl.tex
  2. +5 −1 src/gp4par/make_graphs.cpp
  3. +57 −6 src/greenpak4/Greenpak4Delay.cpp
  4. +10 −0 src/greenpak4/Greenpak4Delay.h
  5. +1 −0 tests/greenpak4/CMakeLists.txt
  6. +96 −0 tests/greenpak4/Ethernet.v
79 changes: 74 additions & 5 deletions doc/gp4-hdl.tex
Original file line number Diff line number Diff line change
@@ -235,7 +235,6 @@ \section{\namestyle{gp4par} Limitations}
\item PGEN mode of LUT4/PGEN block
\item Wake-Sleep
\item DCMP/PWM
\item Edge detector mode of PDELAY/edge detect block
\item Slave SPI
\end{itemize}

@@ -1676,15 +1675,14 @@ \subsection{\tokenstyle{GP\_DELAY}: Programmable Digital Delay Line}

\subsubsection{Introduction}
This primitive corresponds to a programmable digital delay line with four taps. It uniformly delays an incoming digital
waveform by a fixed amount.
waveform by a fixed amount. A glitch filter may be enabled to add an additional ~200 ns delay (PTV dependent) while
rejecting glitches during this period.

For the SLG46620V each tap is nominally 165 ns at 3.3V. The exact range of tap delay values is PTV dependent; see
device datasheet for values.

TODO: is jitter characterized anywhere?

TODO: Add parameter for glitch filter?

\subsubsection{Port Descriptions}

\begin{tabularx}{\textwidth}{lllX}
@@ -1705,6 +1703,8 @@ \subsubsection{Parameter Descriptions}
\thickhline
\tokenstyle{DELAY\_STEPS} & Integer & 3 & Number of delay taps (1-4) \\
\thinhline
\tokenstyle{GLITCH\_FILTER} & Boolean & 1 & True to enable the glitch filter (approximately 200 ns delay) \\
\thinhline
\end{tabularx}

\subsubsection{Verilog Usage Example}
@@ -1713,7 +1713,10 @@ \subsubsection{Verilog Usage Example}

\begin{figure}[h]
\begin{lstlisting}
GP_DELAY #(.DELAY_STEPS(1)) delay(
GP_DELAY #(
.DELAY_STEPS(1),
.GLITCH_FILTER(0)
) delay(
.IN(clk),
.OUT(clk_delayed)
);
@@ -2235,6 +2238,72 @@ \subsubsection{Verilog Usage Example}
\label{gp-dffsri-example}
\end{figure}


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% GP_EDGEDET

\pagebreak
\subsection{\tokenstyle{GP\_EDGEDET}: Edge detector}
\label{gp-edgedet}

%parameter EDGE_DIRECTION = "RISING";
%parameter DELAY_STEPS = 1;
%parameter GLITCH_FILTER = 0;

\subsubsection{Introduction}

This primitive is a monostable delay line with four taps. It can be configured to detect rising edges, falling, or
both. An additional delay can be added for glitch filtering.

For the SLG46620V each tap is nominally 150 ns at 3.3V. The exact range of tap delay values is PTV dependent; see
device datasheet for values.

\subsubsection{Port Descriptions}

\begin{tabularx}{\textwidth}{lllX}
\thinhline
\whenstyle{Port} & \whenstyle{Type} & \whenstyle{Width} & \whenstyle{Function} \\
\thickhline
\tokenstyle{IN} & Input & 1 & Input data. \\
\thinhline
\tokenstyle{OUT} & Output & 1 & Edge detector output. \\
\thinhline
\end{tabularx}

\subsubsection{Parameter Descriptions}

\begin{tabularx}{\textwidth}{lllX}
\thinhline
\whenstyle{Parameter} & \whenstyle{Type} & \whenstyle{Width} & \whenstyle{Function} \\
\thickhline
\tokenstyle{DELAY\_STEPS} & Integer & 3 & Number of delay taps (1-4) \\
\thinhline
\tokenstyle{EDGE\_DIRECTION} & String & & One of ``RISING", ``FALLING", ``BOTH" \\
\thinhline
\tokenstyle{GLITCH\_FILTER} & Boolean & 1 & True to enable the glitch filter (approximately 200 ns delay) \\
\thinhline
\end{tabularx}

\subsubsection{Verilog Usage Example}

The example shown in figure \ref{gp-edgedet-example} drives clk\_edge high for approximately 150 ns each time clk goes
high.

\begin{figure}[h]
\begin{lstlisting}
GP_EDGEDET #(
.DELAY_STEPS(1),
.EDGE_DIRECTION("RISING"),
.GLITCH_FILTER(0)
) edgedet(
.IN(clk),
.OUT(clk_edge)
);
\end{lstlisting}
\caption{Example usage of \tokenstyle{GP\_EDGEDET}}
\label{gp-edgedet-example}
\end{figure}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% GP_IBUF

6 changes: 5 additions & 1 deletion src/gp4par/make_graphs.cpp
Original file line number Diff line number Diff line change
@@ -465,8 +465,12 @@ void MakeDeviceNodes(

//Make device nodes for the delay lines
uint32_t delay_label = AllocateLabel(ngraph, dgraph, lmap, "GP_DELAY");
uint32_t edgedet_label = AllocateLabel(ngraph, dgraph, lmap, "GP_EDGEDET");
for(unsigned int i=0; i<device->GetDelayCount(); i++)
MakeNode(delay_label, device->GetDelay(i), dgraph);
{
auto node = MakeNode(delay_label, device->GetDelay(i), dgraph);
node->AddAlternateLabel(edgedet_label);
}

//Make device nodes for each type of flipflop
uint32_t dff_label = AllocateLabel(ngraph, dgraph, lmap, "GP_DFF");
63 changes: 57 additions & 6 deletions src/greenpak4/Greenpak4Delay.cpp
Original file line number Diff line number Diff line change
@@ -33,6 +33,8 @@ Greenpak4Delay::Greenpak4Delay(
: Greenpak4BitstreamEntity(device, matrix, ibase, obase, cbase)
, m_input(device->GetGround())
, m_delayTap(1)
, m_mode(DELAY)
, m_glitchFilter(false)
{
}

@@ -91,9 +93,38 @@ bool Greenpak4Delay::CommitChanges()
if(ncell == NULL)
return true;

//Delay line
if(ncell->m_type == "GP_DELAY")
m_mode = DELAY;

//Edge detector
else
{
m_mode = RISING_EDGE;

if(ncell->HasParameter("EDGE_DIRECTION"))
{
string dir = ncell->m_parameters["EDGE_DIRECTION"];
if(dir == "RISING")
m_mode = RISING_EDGE;
else if(dir == "FALLING")
m_mode = FALLING_EDGE;
else if(dir == "BOTH")
m_mode = BOTH_EDGE;
else
{
LogError("Invalid delay specifier %s (must be one of RISING, FALLING, BOTH)\n", dir.c_str());
return false;
}
}
}

if(ncell->HasParameter("DELAY_STEPS"))
m_delayTap = atoi(ncell->m_parameters["DELAY_STEPS"].c_str());

if(ncell->HasParameter("GLITCH_FILTER"))
m_glitchFilter = atoi(ncell->m_parameters["GLITCH_FILTER"].c_str()) ? true : false;

return true;
}

@@ -108,16 +139,36 @@ bool Greenpak4Delay::Save(bool* bitstream)
{
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// INPUT BUS

if(!WriteMatrixSelector(bitstream, m_inputBaseWord, m_input))
return false;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// CONFIGURATION

//Mode: for now, hard code to delay (no edge detect supported)
bitstream[m_configBase + 0] = true;
bitstream[m_configBase + 1] = true;
//Mode selector
switch(m_mode)
{
case RISING_EDGE:
bitstream[m_configBase + 0] = false;
bitstream[m_configBase + 1] = false;
break;

case FALLING_EDGE:
bitstream[m_configBase + 0] = true;
bitstream[m_configBase + 1] = false;
break;

case BOTH_EDGE:
bitstream[m_configBase + 0] = false;
bitstream[m_configBase + 1] = true;
break;

case DELAY:
bitstream[m_configBase + 0] = true;
bitstream[m_configBase + 1] = true;
break;
}

//Select the number of delay taps
int ntap = m_delayTap - 1;
@@ -131,8 +182,8 @@ bool Greenpak4Delay::Save(bool* bitstream)
bitstream[m_configBase + 2] = (ntap & 1) ? true : false;
bitstream[m_configBase + 3] = (ntap & 2) ? true : false;

//Output delay (for now, always off)
bitstream[m_configBase + 4] = false;
//Glitch filter
bitstream[m_configBase + 4] = m_glitchFilter;

return true;
}
10 changes: 10 additions & 0 deletions src/greenpak4/Greenpak4Delay.h
Original file line number Diff line number Diff line change
@@ -53,6 +53,16 @@ class Greenpak4Delay : public Greenpak4BitstreamEntity
Greenpak4EntityOutput m_input;

int m_delayTap;

enum modes
{
DELAY,
RISING_EDGE,
FALLING_EDGE,
BOTH_EDGE
} m_mode;

bool m_glitchFilter;
};

#endif //Greenpak4Delay_h
1 change: 1 addition & 0 deletions tests/greenpak4/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -27,6 +27,7 @@ add_greenpak4_test(Bargraph)
add_greenpak4_test(Blinky)
add_greenpak4_test(Dac)
add_greenpak4_test(Delay)
add_greenpak4_test(Ethernet)
add_greenpak4_test(Inverters)
add_greenpak4_test(Location)
add_greenpak4_test(Loop)
96 changes: 96 additions & 0 deletions tests/greenpak4/Ethernet.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,96 @@
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/

`default_nettype none

/**
@brief Minimal 10baseT autonegotiation
*/
module Ethernet(rst_done, clk_debug, txd);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations

(* LOC = "P20" *)
output reg rst_done = 0;

(* LOC = "P19" *)
output wire clk_debug;

(* LOC = "P18" *)
output wire txd;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System reset stuff

//Power-on reset flag
wire por_done;
GP_POR #(.POR_TIME(500)) por (.RST_DONE(por_done));

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Clock source - 2 MHz RC oscillator

//500 ns per cycle

wire clk_hardip;
wire clk_fabric;
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("2M"),
.PRE_DIV(1),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(clk_hardip),
.CLKOUT_FABRIC(clk_fabric)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual logic

reg pulse_en = 0;

always @(posedge clk_fabric) begin
pulse_en <= ~pulse_en;
end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Edge detector for producing ~150 ns FLPs

wire pulse_out;
GP_EDGEDET #(
.DELAY_STEPS(1),
.EDGE_DIRECTION("RISING"),
.GLITCH_FILTER(0)
) delay(
.IN(pulse_en),
.OUT(pulse_out)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Debug outputs

//Detect when the system reset has completed
always @(posedge clk_fabric)
rst_done <= 1;

assign clk_debug = clk_fabric;
assign txd = pulse_out;

endmodule