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phaser: comment out stpl test
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jordens committed Oct 11, 2016
1 parent 2b1cca2 commit bae5b73
Showing 1 changed file with 8 additions and 7 deletions.
15 changes: 8 additions & 7 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -544,13 +544,14 @@ def __init__(self, cpu_type="or1k", **kwargs):
# while at 5 GBps, take every second sample... FIXME
self.comb += conv.eq(Cat(ch.o[::2]))

# short transport layer test pattern
self.comb += [
self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123),
self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567),
self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab),
self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef)
]
if False:
# short transport layer test pattern
self.comb += [
self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123),
self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567),
self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab),
self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef)
]

self.comb += jesd_sync.eq(self.ad9154.jesd_sync)

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