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  • 15 commits
  • 10 files changed
  • 1 contributor

Commits on Sep 30, 2016

  1. Copy the full SHA
    920c5a9 View commit details
  2. ad9154: status readout

    jordens committed Sep 30, 2016
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    bf31363 View commit details
  3. Revert "kc705: remove rtio_external_clk for phaser"

    This reverts commit d500288.
    jordens committed Sep 30, 2016
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    f340c1f View commit details
  4. Revert "kc705: feed rtio_external_clock directly"

    This reverts commit 8dc7825.
    jordens committed Sep 30, 2016
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    3dbb3d6 View commit details
  5. Revert "phase: wire up clocking differently"

    This reverts commit ad9cc45.
    jordens committed Sep 30, 2016
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    a7d9edd View commit details
  6. Revert "kc705: mirror clk200 at user_sma_clock_p"

    This reverts commit 7f0dffd.
    jordens committed Sep 30, 2016
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    497d9e7 View commit details
  7. Revert "kc705: single ended rtio_external_clk"

    This reverts commit a9426d9.
    jordens committed Sep 30, 2016
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    c2401a3 View commit details
  8. ad9516: 2000 MHz clock

    jordens committed Sep 30, 2016
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    dfde0d3 View commit details
  9. phaser: test clock dist

    jordens committed Sep 30, 2016
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    ef667ae View commit details
  10. phaser: test freqs

    jordens committed Sep 30, 2016
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    0149338 View commit details
  11. ad9154: iostandards

    jordens committed Sep 30, 2016
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    65f848e View commit details
  12. phaser: drop clock monitor

    jordens committed Sep 30, 2016
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    869335f View commit details
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    0e9e142 View commit details
  14. phaser: no separate i2c

    jordens committed Sep 30, 2016
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    3ff0241 View commit details
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14 changes: 10 additions & 4 deletions artiq/examples/phaser/device_db.pyon
Original file line number Diff line number Diff line change
@@ -30,28 +30,34 @@
"class": "TTLOut",
"arguments": {"channel": 1}
},
"sysref": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 2}
},
"sawg0": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 2, "parallelism": 4}
"arguments": {"channel_base": 3, "parallelism": 4}
},
"sawg1": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 5, "parallelism": 4}
"arguments": {"channel_base": 6, "parallelism": 4}
},
"sawg2": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 8, "parallelism": 4}
"arguments": {"channel_base": 9, "parallelism": 4}
},
"sawg3": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 11, "parallelism": 4}
"arguments": {"channel_base": 12, "parallelism": 4}
}
}
9 changes: 4 additions & 5 deletions artiq/gateware/phaser.py
Original file line number Diff line number Diff line change
@@ -2,11 +2,6 @@


fmc_adapter_io = [
("ad9154_i2c", 0,
Subsignal("scl", Pins("HPC:IIC_SCL")),
Subsignal("sda", Pins("HPC:IIC_SDA")),
IOStandard("LVCMOS25")
),
("ad9154_spi", 0,
# AD9154 should give control of SPI to FMC when USB cable is unplugged,
# It's the case, but the PIC18F24J50 is introducing noise on SPI SCK
@@ -26,18 +21,22 @@
("ad9154_refclk", 0,
Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
IOStandard("LVDS_25"),
),
("ad9154_sysref", 0,
Subsignal("p", Pins("HPC:LA00_CC_P")),
Subsignal("n", Pins("HPC:LA00_CC_N")),
IOStandard("LVDS_25"),
),
("ad9154_sync", 0,
Subsignal("p", Pins("HPC:LA01_CC_P")),
Subsignal("n", Pins("HPC:LA01_CC_N")),
IOStandard("LVDS_25"),
),
("ad9154_sync2", 0,
Subsignal("p", Pins("HPC:LA02_P")),
Subsignal("n", Pins("HPC:LA02_N")),
IOStandard("LVDS_25"),
),
("ad9154_jesd", 0, # AD9154's SERIND7
Subsignal("txp", Pins("HPC:DP0_C2M_P")),
32 changes: 22 additions & 10 deletions artiq/gateware/rtio/phy/ttl_serdes_7series.py
Original file line number Diff line number Diff line change
@@ -4,28 +4,35 @@


class _OSERDESE2_8X(Module):
def __init__(self, pad):
def __init__(self, pad, pad_n=None):
self.o = Signal(8)
self.t_in = Signal()
self.t_out = Signal()

# # #

o = self.o
pad_o = Signal()
self.specials += Instance("OSERDESE2",
p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
o_OQ=pad, o_TQ=self.t_out,
o_OQ=pad_o, o_TQ=self.t_out,
i_CLK=ClockSignal("rtiox4"),
i_CLKDIV=ClockSignal("rio_phy"),
i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3],
i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7],
i_TCE=1, i_OCE=1, i_RST=0,
i_T1=self.t_in)
if pad_n is None:
self.comb += pad.eq(pad_o)
else:
self.specials += Instance("OBUFDS",
i_I=pad_o,
o_O=pad, o_OB=pad_n)


class _IOSERDESE2_8X(Module):
def __init__(self, pad):
def __init__(self, pad, pad_n=None):
self.o = Signal(8)
self.i = Signal(8)
self.oe = Signal()
@@ -47,24 +54,29 @@ def __init__(self, pad):
i_CLKDIV=ClockSignal("rio_phy"))
oserdes = _OSERDESE2_8X(pad_o)
self.submodules += oserdes
self.specials += Instance("IOBUF",
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad)
if pad_n is None:
self.specials += Instance("IOBUF",
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad)
else:
self.specials += Instance("IOBUFDS",
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad, io_IOB=pad_n)
self.comb += [
oserdes.t_in.eq(~self.oe),
oserdes.o.eq(self.o)
]


class Output_8X(ttl_serdes_generic.Output):
def __init__(self, pad):
serdes = _OSERDESE2_8X(pad)
def __init__(self, pad, pad_n=None):
serdes = _OSERDESE2_8X(pad, pad_n)
self.submodules += serdes
ttl_serdes_generic.Output.__init__(self, serdes)


class Inout_8X(ttl_serdes_generic.Inout):
def __init__(self, pad):
serdes = _IOSERDESE2_8X(pad)
def __init__(self, pad, pad_n=None):
serdes = _IOSERDESE2_8X(pad, pad_n)
self.submodules += serdes
ttl_serdes_generic.Inout.__init__(self, serdes)
83 changes: 77 additions & 6 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -9,6 +9,7 @@
from migen.build.xilinx.vivado import XilinxVivadoToolchain
from migen.build.xilinx.ise import XilinxISEToolchain
from migen.fhdl.specials import Keep
from migen.genlib.io import DifferentialInput

from misoc.interconnect.csr import *
from misoc.interconnect import wishbone
@@ -39,6 +40,13 @@ def __init__(self, platform, rtio_internal_clk):
self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)


rtio_external_clk = Signal()
user_sma_clock = platform.request("user_sma_clock")
platform.add_period_constraint(user_sma_clock.p, 8.0)
self.specials += Instance("IBUFDS",
i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
o_O=rtio_external_clk)

pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
@@ -49,7 +57,7 @@ def __init__(self, platform, rtio_internal_clk):

p_REF_JITTER1=0.01,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

@@ -144,8 +152,8 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.register_kernel_cpu_csrdevice("i2c")
self.config["I2C_BUS_COUNT"] = 1

def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
def add_rtio(self, rtio_channels, crg=_RTIOCRG):
self.submodules.rtio_crg = crg(self.platform, self.crg.cd_sys.clk)
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio")
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
@@ -383,6 +391,56 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width


class _PhaserCRG(Module, AutoCSR):
def __init__(self, platform, rtio_internal_clk):
self._clock_sel = CSRStorage()
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)

refclk_pads = platform.request("ad9154_refclk")
platform.add_period_constraint(refclk_pads.p, 2.)
refclk = Signal()
refclk = Signal()
self.clock_domains.cd_refclk = ClockDomain()
self.specials += [
Instance("IBUFDS_GTE2", i_CEB=0,
i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk),
Instance("BUFG", i_I=refclk, o_O=self.cd_refclk.clk),
]

pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
self.specials += [
Instance("PLLE2_ADV",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,

p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=2.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=refclk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

# VCO @ 1GHz when using 500MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=4,
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,

o_CLKFBOUT=rtio_clk,

p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=rtiox4_clk,
),
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),

AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self._pll_locked.status)
]


class Phaser(_NIST_Ions):
csr_map = {}
csr_map.update(_NIST_Ions.csr_map)
@@ -394,8 +452,17 @@ def __init__(self, cpu_type="or1k", **kwargs):
platform = self.platform
platform.add_extension(phaser.fmc_adapter_io)

user_sma_clock = platform.request("user_sma_clock_p")
self.comb += user_sma_clock.eq(self.crg.clk200_se)
sysref_pads = platform.request("ad9154_sysref")
#sysref = Signal()
#self.specials += DifferentialInput(
# sysref_pads.p, sysref_pads.n, sysref)
sync_pads = platform.request("ad9154_sync")
sync = Signal()
self.specials += DifferentialInput(
sync_pads.p, sync_pads.n, sync)

#for i in range(4):
# jesd_pads = platform.request("ad9154_jesd", i)

rtio_channels = []

@@ -408,6 +475,10 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))

phy = ttl_serdes_7series.Inout_8X(sysref_pads.p, sysref_pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))

self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)

ad9154_spi = self.platform.request("ad9154_spi")
@@ -438,7 +509,7 @@ def __init__(self, cpu_type="or1k", **kwargs):

self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
self.add_rtio(rtio_channels, _PhaserCRG)


def main():
2 changes: 1 addition & 1 deletion artiq/runtime/Makefile
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ PYTHON ?= python3.5

OBJECTS := isr.o clock.o rtiocrg.o flash_storage.o mailbox.o \
session.o log.o analyzer.o moninj.o net_server.o bridge_ctl.o \
ksupport_data.o kloader.o test_mode.o main.o ad9154.o ad9516.o
ksupport_data.o kloader.o test_mode.o main.o ad9154.o
OBJECTS_KSUPPORT := ksupport.o artiq_personality.o mailbox.o \
bridge.o rtio.o dds.o i2c.o

26 changes: 17 additions & 9 deletions artiq/runtime/ad9154.c
Original file line number Diff line number Diff line change
@@ -18,31 +18,39 @@ void ad9154_spi_config(void)
ad9154_spi_half_duplex_write(0);
ad9154_spi_clk_div_write_write(11);
ad9154_spi_clk_div_read_write(11);
ad9154_spi_cs_write(CONFIG_AD9154_DAC_CS);
ad9154_spi_xfer_len_write_write(24);
ad9154_spi_xfer_len_read_write(0);
ad9154_spi_cs_write(CONFIG_AD9154_DAC_CS);
ad9154_spi_offline_write(0);
}

#define AD9154_READ (1 << 15)
#define AD9154_XFER(w) ((w) << 13)
#define AD9_READ (1 << 15)
#define AD9_XFER(w) ((w) << 13)

static void ad9154_xfer(uint16_t addr, uint8_t data)
void ad9154_write(uint16_t addr, uint8_t data)
{
ad9154_spi_data_write_write(
((AD9154_XFER(0) | addr) << 16) | (data << 8));
((AD9_XFER(0) | addr) << 16) | (data << 8));
while (ad9154_spi_pending_read());
while (ad9154_spi_active_read());
}

void ad9154_write(uint16_t addr, uint8_t data)
uint8_t ad9154_read(uint16_t addr)
{
ad9154_xfer(addr, data);
ad9154_write(AD9_READ | addr, 0);
return ad9154_spi_data_read_read();
}

uint8_t ad9154_read(uint16_t addr)
void ad9516_write(uint16_t addr, uint8_t data)
{
ad9154_spi_cs_write(CONFIG_AD9154_CLK_CS);
ad9154_write(addr, data);
ad9154_spi_cs_write(CONFIG_AD9154_DAC_CS);
}

uint8_t ad9516_read(uint16_t addr)
{
ad9154_xfer(AD9154_READ | addr, 0);
ad9516_write(AD9_READ | addr, 0);
return ad9154_spi_data_read_read();
}

5 changes: 4 additions & 1 deletion artiq/runtime/ad9154.h
Original file line number Diff line number Diff line change
@@ -4,11 +4,14 @@
#ifdef CONFIG_AD9154_DAC_CS

#include "ad9154_reg.h"
#include "ad9516_reg.h"

void ad9154_spi_config(void);
void ad9154_write(uint16_t addr, uint8_t data);
uint8_t ad9154_read(uint16_t addr);

#endif
void ad9516_write(uint16_t addr, uint8_t data);
uint8_t ad9516_read(uint16_t addr);

#endif
#endif
49 changes: 0 additions & 49 deletions artiq/runtime/ad9516.c

This file was deleted.

14 changes: 0 additions & 14 deletions artiq/runtime/ad9516.h

This file was deleted.

243 changes: 178 additions & 65 deletions artiq/runtime/test_mode.c
Original file line number Diff line number Diff line change
@@ -20,7 +20,6 @@
#include "clock.h"
#include "test_mode.h"
#include "ad9154.h"
#include "ad9516.h"

#ifdef CSR_LEDS_BASE
static void leds(char *value)
@@ -570,10 +569,139 @@ static void fs_test(void)

#ifdef CONFIG_AD9154_DAC_CS

static void dac_test(void)
static void ad9154_prbs(uint8_t p, uint32_t t)
{
uint32_t i;
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p));
ad9154_write(AD9154_PHY_PRBS_TEST_EN, 0xff);
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p) | AD9154_PHY_TEST_RESET_SET(1));
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p));

ad9154_write(AD9154_PHY_PRBS_TEST_THRESHOLD_LOBITS, t);
ad9154_write(AD9154_PHY_PRBS_TEST_THRESHOLD_MIDBITS, t >> 8);
ad9154_write(AD9154_PHY_PRBS_TEST_THRESHOLD_MIDBITS, t >> 16);

ad9154_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_PRBS_PAT_SEL_SET(p));
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p) | AD9154_PHY_TEST_START_SET(1));
busywait_us(500*1000);
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_PRBS_PAT_SEL_SET(p));

printf("prbs status: 0x%02x\n", ad9154_read(AD9154_PHY_PRBS_TEST_STATUS));

for(i=0; i<8; i++) {
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_SRC_ERR_CNT_SET(i));
printf("prbs errors[%d]: 0x%08x\n", i,
ad9154_read(AD9154_PHY_PRBS_TEST_ERRCNT_LOBITS) |
(ad9154_read(AD9154_PHY_PRBS_TEST_ERRCNT_MIDBITS) << 8) |
(ad9154_read(AD9154_PHY_PRBS_TEST_ERRCNT_HIBITS) << 16));
}
}

static void ad9154_print_temp(void)
{
ad9154_write(AD9154_DIE_TEMP_CTRL0, AD9154_AUXADC_RESERVED_SET(0x10) |
AD9154_AUXADC_ENABLE_SET(1));
busywait_us(1000);
ad9154_write(AD9154_DIE_TEMP_UPDATE, 1);
busywait_us(1000);
printf("temp_code %d\n", ad9154_read(AD9154_DIE_TEMP0) |
(ad9154_read(AD9154_DIE_TEMP1) << 8));
ad9154_write(AD9154_DIE_TEMP_CTRL0, AD9154_AUXADC_RESERVED_SET(0x10) |
AD9154_AUXADC_ENABLE_SET(0));
}

static void ad9154_print_status(void)
{
uint32_t p, t, i;
uint32_t x;

x = ad9154_read(AD9154_IRQ_STATUS0);
printf("LANEFIFOERR: %d, SERPLLLOCK: %d, SERPLLLOST: %d, "
"DACPLLLOCK: %d, DACPLLLOST: %d\n",
AD9154_LANEFIFOERR_GET(x), AD9154_SERPLLLOCK_GET(x),
AD9154_SERPLLLOST_GET(x), AD9154_DACPLLLOCK_GET(x),
AD9154_DACPLLLOST_GET(x));
x = ad9154_read(AD9154_IRQ_STATUS1);
printf("PRBS0: %d, PRBS1: %d, PRBS2: %d, PRBS3: %d\n",
AD9154_PRBS0_GET(x), AD9154_PRBS1_GET(x),
AD9154_PRBS2_GET(x), AD9154_PRBS3_GET(x));
x = ad9154_read(AD9154_IRQ_STATUS2);
printf("SYNC_TRIP0: %d, SYNC_WLIM0: %d, SYNC_ROTATE0: %d, "
"SYNC_LOCK0: %d, NCO_ALIGN0: %d, BLNKDONE0: %d, "
"PDPERR0: %d\n",
AD9154_SYNC_TRIP0_GET(x), AD9154_SYNC_WLIM0_GET(x),
AD9154_SYNC_ROTATE0_GET(x), AD9154_SYNC_LOCK0_GET(x),
AD9154_NCO_ALIGN0_GET(x), AD9154_BLNKDONE0_GET(x),
AD9154_PDPERR0_GET(x));
x = ad9154_read(AD9154_IRQ_STATUS3);
printf("SYNC_TRIP1: %d, SYNC_WLIM1: %d, SYNC_ROTATE1: %d, "
"SYNC_LOCK1: %d, NCO_ALIGN1: %d, BLNKDONE1: %d, "
"PDPERR1: %d\n",
AD9154_SYNC_TRIP1_GET(x), AD9154_SYNC_WLIM1_GET(x),
AD9154_SYNC_ROTATE1_GET(x), AD9154_SYNC_LOCK1_GET(x),
AD9154_NCO_ALIGN1_GET(x), AD9154_BLNKDONE1_GET(x),
AD9154_PDPERR1_GET(x));
x = ad9154_read(AD9154_JESD_CHECKS);
printf("ERR_INTSUPP: %d, ERR_SUBCLASS: %d, ERR_KUNSUPP: %d, "
"ERR_JESDBAD: %d, ERR_WINLIMIT: %d, ERR_DLYOVER: %d\n",
AD9154_ERR_INTSUPP_GET(x), AD9154_ERR_SUBCLASS_GET(x),
AD9154_ERR_KUNSUPP_GET(x), AD9154_ERR_JESDBAD_GET(x),
AD9154_ERR_WINLIMIT_GET(x), AD9154_ERR_DLYOVER_GET(x));

x = ad9154_read(AD9154_SYNC_LASTERR_H);
printf("SYNC_LASTERR: 0x%04x\n", ad9154_read(AD9154_SYNC_LASTERR_L) |
(AD9154_LASTERROR_H_GET(x) << 8));
printf("SYNC_LASTOVER: %d, SYNC_LASTUNDER: %d\n",
AD9154_LASTOVER_GET(x), AD9154_LASTUNDER_GET(x));
x = ad9154_read(AD9154_SYNC_STATUS);
printf("SYNC_TRIP: %d, SYNC_WLIM: %d, SYNC_ROTATE: %d, "
"SYNC_LOCK: %d, SYNC_BUSY: %d\n",
AD9154_SYNC_TRIP_GET(x), AD9154_SYNC_WLIM_GET(x),
AD9154_SYNC_ROTATE_GET(x), AD9154_SYNC_LOCK_GET(x),
AD9154_SYNC_BUSY_GET(x));

printf("LANE_FIFO_FULL: 0x%02x\n", ad9154_read(AD9154_FIFO_STATUS_REG_0));
printf("LANE_FIFO_EMPTY: 0x%02x\n", ad9154_read(AD9154_FIFO_STATUS_REG_1));
printf("DID_REG: 0x%02x\n", ad9154_read(AD9154_DID_REG));
printf("BID_REG: 0x%02x\n", ad9154_read(AD9154_BID_REG));
printf("SCR_L_REG: 0x%02x\n", ad9154_read(AD9154_SCR_L_REG));
printf("F_REG: 0x%02x\n", ad9154_read(AD9154_F_REG));
printf("K_REG: 0x%02x\n", ad9154_read(AD9154_K_REG));
printf("M_REG: 0x%02x\n", ad9154_read(AD9154_M_REG));
printf("CS_N_REG: 0x%02x\n", ad9154_read(AD9154_CS_N_REG));
printf("NP_REG: 0x%02x\n", ad9154_read(AD9154_NP_REG));
printf("S_REG: 0x%02x\n", ad9154_read(AD9154_S_REG));
printf("HD_CF_REG: 0x%02x\n", ad9154_read(AD9154_HD_CF_REG));
printf("RES1_REG: 0x%02x\n", ad9154_read(AD9154_RES1_REG));
printf("RES2_REG: 0x%02x\n", ad9154_read(AD9154_RES2_REG));
printf("LIDx_REG: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
ad9154_read(AD9154_LID0_REG), ad9154_read(AD9154_LID1_REG),
ad9154_read(AD9154_LID2_REG), ad9154_read(AD9154_LID3_REG),
ad9154_read(AD9154_LID4_REG), ad9154_read(AD9154_LID5_REG),
ad9154_read(AD9154_LID6_REG), ad9154_read(AD9154_LID7_REG));
printf("CHECKSUMx_REG: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
ad9154_read(AD9154_CHECKSUM0_REG), ad9154_read(AD9154_CHECKSUM1_REG),
ad9154_read(AD9154_CHECKSUM2_REG), ad9154_read(AD9154_CHECKSUM3_REG),
ad9154_read(AD9154_CHECKSUM4_REG), ad9154_read(AD9154_CHECKSUM5_REG),
ad9154_read(AD9154_CHECKSUM6_REG), ad9154_read(AD9154_CHECKSUM7_REG));
printf("COMPSUMx_REG: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
ad9154_read(AD9154_COMPSUM0_REG), ad9154_read(AD9154_COMPSUM1_REG),
ad9154_read(AD9154_COMPSUM2_REG), ad9154_read(AD9154_COMPSUM3_REG),
ad9154_read(AD9154_COMPSUM4_REG), ad9154_read(AD9154_COMPSUM5_REG),
ad9154_read(AD9154_COMPSUM6_REG), ad9154_read(AD9154_COMPSUM7_REG));
printf("BADDISPARITY: 0x%02x\n", ad9154_read(AD9154_BADDISPARITY));
printf("NITDISPARITY: 0x%02x\n", ad9154_read(AD9154_NIT_W));
printf("UNEXPECTEDCONTROL: 0x%02x\n", ad9154_read(AD9154_UNEXPECTEDCONTROL_W));

ad9154_print_temp();
}

static void dac_test(void)
{
int i;
ad9154_spi_config();

/* reset */
@@ -593,6 +721,8 @@ static void dac_test(void)
AD9154_PD_DAC0_SET(0) | AD9154_PD_DAC1_SET(0) |
AD9154_PD_DAC2_SET(0) | AD9154_PD_DAC3_SET(0) |
AD9154_PD_BG_SET(0));
ad9154_write(AD9154_TXENMASK1, AD9154_DACA_MASK_SET(0) |
AD9154_DACB_MASK_SET(0)); /* TX not controlled by TXEN pins */
ad9154_write(AD9154_CLKCFG0,
AD9154_REF_CLKDIV_EN_SET(0) | AD9154_RF_SYNC_EN_SET(1) |
AD9154_DUTY_EN_SET(1) | AD9154_PD_CLK_REC_SET(0) |
@@ -609,6 +739,7 @@ static void dac_test(void)
ad9154_write(AD9154_SPI_PAGEINDX, 0x3); /* A and B dual */

ad9154_write(AD9154_INTERP_MODE, 0); /* 1x */
ad9154_write(AD9154_MIX_MODE, 0);
ad9154_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)); /* s16 */
ad9154_write(AD9154_DATAPATH_CTRL,
AD9154_I_TO_Q_SET(0) | AD9154_SEL_SIDEBAND_SET(0) |
@@ -653,6 +784,9 @@ static void dac_test(void)

ad9154_write(AD9154_MASTER_PD, 0x00);
ad9154_write(AD9154_PHY_PD, 0x0f); /* power down lanes 0-3 */
ad9154_write(AD9154_GENERIC_PD,
AD9154_PD_SYNCOUT0B_SET(0) |
AD9154_PD_SYNCOUT1B_SET(0));
ad9154_write(AD9154_GENERAL_JRX_CTRL_0,
AD9154_LINK_EN_SET(0) | AD9154_LINK_PAGE_SET(0) |
AD9154_LINK_MODE_SET(0) | AD9154_CHECKSUM_MODE_SET(0));
@@ -668,11 +802,35 @@ static void dac_test(void)
AD9154_SUBCLASSV_SET(1));
ad9154_write(AD9154_ILS_S, AD9154_S_1_SET(1 - 1) | AD9154_JESDV_SET(1));
ad9154_write(AD9154_ILS_HD_CF, AD9154_HD_SET(0) | AD9154_CF_SET(0));
ad9154_write(AD9154_ILS_CHECKSUM, 0xde); /* TODO */
ad9154_write(AD9154_ILS_CHECKSUM,
0x00 + 0x00 + 0x00 + 1 + (4 - 1) + /* DID BID LID SCR L */
(2 - 1) + (16 - 1) + (4 - 1) + (16 - 1) + /* F K M N */
1 + (16 - 1) + 1 + (1 - 1) + 0 /* SUBC NP JESDV S HD */);
ad9154_write(AD9154_LANEDESKEW, 0xf0);
for(i=0; i<8; i++) {
ad9154_write(AD9154_BADDISPARITY, AD9154_RST_IRQ_DIS_SET(0) |
AD9154_DISABLE_ERR_CNTR_DIS_SET(0) |
AD9154_RST_ERR_CNTR_DIS_SET(1) | AD9154_LANE_ADDR_DIS_SET(i));
ad9154_write(AD9154_BADDISPARITY, AD9154_RST_IRQ_DIS_SET(0) |
AD9154_DISABLE_ERR_CNTR_DIS_SET(0) |
AD9154_RST_ERR_CNTR_DIS_SET(0) | AD9154_LANE_ADDR_DIS_SET(i));
ad9154_write(AD9154_NIT_W, AD9154_RST_IRQ_NIT_SET(0) |
AD9154_DISABLE_ERR_CNTR_NIT_SET(0) |
AD9154_RST_ERR_CNTR_NIT_SET(1) | AD9154_LANE_ADDR_NIT_SET(i));
ad9154_write(AD9154_NIT_W, AD9154_RST_IRQ_NIT_SET(0) |
AD9154_DISABLE_ERR_CNTR_NIT_SET(0) |
AD9154_RST_ERR_CNTR_NIT_SET(0) | AD9154_LANE_ADDR_NIT_SET(i));
ad9154_write(AD9154_UNEXPECTEDCONTROL_W, AD9154_RST_IRQ_UCC_SET(0) |
AD9154_DISABLE_ERR_CNTR_UCC_SET(0) |
AD9154_RST_ERR_CNTR_UCC_SET(1) | AD9154_LANE_ADDR_UCC_SET(i));
ad9154_write(AD9154_BADDISPARITY, AD9154_RST_IRQ_UCC_SET(0) |
AD9154_DISABLE_ERR_CNTR_UCC_SET(0) |
AD9154_RST_ERR_CNTR_UCC_SET(0) | AD9154_LANE_ADDR_UCC_SET(i));
}
ad9154_write(AD9154_CTRLREG1, 2); /* F */
ad9154_write(AD9154_LANEENABLE, 0xf0);


ad9154_write(AD9154_TERM_BLK1_CTRLREG0, 1);
ad9154_write(AD9154_TERM_BLK2_CTRLREG0, 1);
ad9154_write(AD9154_SERDES_SPI_REG, 1);
@@ -748,6 +906,7 @@ static void dac_test(void)
ad9154_write(AD9154_LMFC_DELAY_1, 0);
ad9154_write(AD9154_LMFC_VAR_0, 0x0a); /* receive buffer delay */
ad9154_write(AD9154_LMFC_VAR_1, 0x0a);
ad9154_write(AD9154_SYNC_ERRWINDOW, 0); /* +- 1/2 DAC clock */
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1));
ad9154_write(AD9154_SYNC_CONTROL,
@@ -770,50 +929,10 @@ static void dac_test(void)
AD9154_LINK_MODE_SET(0) | AD9154_CHECKSUM_MODE_SET(0));

busywait_us(500*1000);

p = 2; /* prbs31 */
t = 10; /* threshold */

ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p));
ad9154_write(AD9154_PHY_PRBS_TEST_EN, 0xff);
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p) | AD9154_PHY_TEST_RESET_SET(1));
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p));

ad9154_write(AD9154_PHY_PRBS_TEST_THRESHOLD_LOBITS, t);
ad9154_write(AD9154_PHY_PRBS_TEST_THRESHOLD_MIDBITS, t >> 8);
ad9154_write(AD9154_PHY_PRBS_TEST_THRESHOLD_MIDBITS, t >> 16);

ad9154_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_PRBS_PAT_SEL_SET(p));
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL,
AD9154_PHY_PRBS_PAT_SEL_SET(p) | AD9154_PHY_TEST_START_SET(1));
busywait_us(500*1000);
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_PRBS_PAT_SEL_SET(p));

printf("prbs status: 0x%02x\n", ad9154_read(AD9154_PHY_PRBS_TEST_STATUS));

for(i=0; i<8; i++) {
ad9154_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_SRC_ERR_CNT_SET(i));
printf("prbs errors[%d]: 0x%08x\n", i,
ad9154_read(AD9154_PHY_PRBS_TEST_ERRCNT_LOBITS) |
(ad9154_read(AD9154_PHY_PRBS_TEST_ERRCNT_MIDBITS) << 8) |
(ad9154_read(AD9154_PHY_PRBS_TEST_ERRCNT_HIBITS) << 16));
}


ad9154_write(AD9154_DIE_TEMP_CTRL0, AD9154_AUXADC_RESERVED_SET(0x10) |
AD9154_AUXADC_ENABLE_SET(1));
busywait_us(1000);
ad9154_write(AD9154_DIE_TEMP_UPDATE, 1);
busywait_us(1000);
printf("temp_code %d\n", ad9154_read(AD9154_DIE_TEMP0) |
(ad9154_read(AD9154_DIE_TEMP1) << 8));
ad9154_write(AD9154_DIE_TEMP_CTRL0, AD9154_AUXADC_RESERVED_SET(0x10) |
AD9154_AUXADC_ENABLE_SET(0));
// ad9154_prbs(2, 100); /* prbs32 */
}


static void dac_test_xfer(char *addr, char *data)
{
char *c;
@@ -844,13 +963,9 @@ static void dac_test_xfer(char *addr, char *data)
ad9154_write(addr2, data2);
}

#endif

#ifdef CONFIG_AD9154_DAC_CS

static void clk_test(void)
{
ad9516_spi_config();
ad9154_spi_config();

/* reset */
ad9516_write(AD9516_SERIAL_PORT_CONFIGURATION,
@@ -875,16 +990,17 @@ static void clk_test(void)
* N=16 bits/converter
* NB=16 bits/sample
* pclock=250MHz
* fclock=500MHz
* fdata=500MHz
* fline=10GHz
* deviceclock_fpga=500MHz
* deviceclock_dac=2000MHz
*/

/* clk=500MHz */
/* clk=2000MHz */

/* use clk input, dclk=clk/2 */
/* use clk input, dclk=clk/4 */
ad9516_write(AD9516_PFD_AND_CHARGE_PUMP, AD9516_PLL_POWER_DOWN);
ad9516_write(AD9516_VCO_DIVIDER, 0);
ad9516_write(AD9516_VCO_DIVIDER, 2);
ad9516_write(AD9516_INPUT_CLKS, 0*AD9516_SELECT_VCO_OR_CLK |
0*AD9516_BYPASS_VCO_DIVIDER);

@@ -907,9 +1023,9 @@ static void clk_test(void)
0*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
0*AD9516_OUT9_SELECT_LVDS_CMOS);

/* sysref f_data*S/(K*F), dclk/16 */
ad9516_write(AD9516_DIVIDER_3_0, 7*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
7*AD9516_DIVIDER_3_LOW_CYCLES_1);
/* sysref f_data*S/(K*F), dclk/32 */
ad9516_write(AD9516_DIVIDER_3_0, 15*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
15*AD9516_DIVIDER_3_LOW_CYCLES_1);
ad9516_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1);
ad9516_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC |
0*AD9516_DIVIDER_3_BYPASS_1 | 1*AD9516_DIVIDER_3_BYPASS_2);
@@ -983,13 +1099,12 @@ static void help(void)
puts("fsremove <k> - remove a key-value record from flash storage");
puts("fstest - run flash storage tests. WARNING: erases the storage area");
#endif
#ifdef CONFIG_AD9154_CLK_CS
#ifdef CONFIG_AD9154_DAC_CS
puts("clktest - test AD9516 CLK on FMC");
puts("clkxfer <a> <d?> - SPI read/write AD9516 CLK on FMC");
#endif
#ifdef CONFIG_AD9154_DAC_CS
puts("dactest - test AD9154 DAC on FMC");
puts("dacxfer <a> <d?> - SPI read/write AD9154 DAC on FMC");
puts("dacstatus - DAC status");
#endif
}

@@ -1081,14 +1196,12 @@ static void do_command(char *c)
else if(strcmp(token, "fstest") == 0) fs_test();
#endif

#ifdef CONFIG_AD9154_CLK_CS
#ifdef CONFIG_AD9154_DAC_CS
else if(strcmp(token, "clktest") == 0) clk_test();
else if(strcmp(token, "clkxfer") == 0) clk_test_xfer(get_token(&c), get_token(&c));
#endif

#ifdef CONFIG_AD9154_DAC_CS
else if(strcmp(token, "dactest") == 0) dac_test();
else if(strcmp(token, "dacxfer") == 0) dac_test_xfer(get_token(&c), get_token(&c));
else if(strcmp(token, "dacstatus") == 0) ad9154_print_status();
#endif

else if(strcmp(token, "") != 0)