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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 4ea3dea217ed
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Oct 14, 2016

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    e400f8d View commit details
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    4ea3dea View commit details
Showing with 5 additions and 5 deletions.
  1. +5 −5 artiq/gateware/targets/kc705.py
10 changes: 5 additions & 5 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -467,9 +467,8 @@ def __init__(self, platform):
qpll, platform.request("ad9154_jesd", i), fabric_freq)
platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO
platform.add_false_path_constraints(
self.cd_jesd.clk,
phy.gtx.cd_tx.clk)
for clk in self.cd_jesd.clk, refclk_pads.p, self.refclk:
platform.add_false_path_constraints(clk, phy.gtx.cd_tx.clk)
phys.append(phy)
to_jesd = ClockDomainsRenamer("jesd")
self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings,
@@ -511,10 +510,11 @@ def __init__(self, platform):

x = Signal()
y = Signal()
self.sync.jesd += x.eq(~x)
z = Signal()
self.sync.jesd += x.eq(~x), z.eq(x == y)
self.sync.rio_phy += y.eq(x)
for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
self.comb += conv.eq(Mux(x != y, Cat(ch.o[:2]), Cat(ch.o[2:])))
self.sync.jesd += conv.eq(Mux(z, Cat(ch.o[:2]), Cat(ch.o[2:])))


class Phaser(_NIST_Ions):