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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 54aa6387562b
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  • 4 commits
  • 6 files changed
  • 1 contributor

Commits on Oct 1, 2016

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    5b1f562 View commit details

Commits on Oct 2, 2016

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    9e77861 View commit details
  2. sawg: missing import

    jordens committed Oct 2, 2016
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    8076581 View commit details
  3. sawg: type fixes

    jordens committed Oct 2, 2016
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    54aa638 View commit details
7 changes: 4 additions & 3 deletions artiq/coredevice/sawg.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from artiq.language.core import kernel, now_mu
from artiq.coredevice.rtio import rtio_output
from artiq.language.types import TInt32, TFloat


class SAWG:
@@ -37,7 +38,7 @@ def set_amplitude(self, amplitude: TFloat):
:param amplitude: DDS amplitude relative to full-scale.
"""
self.set_amplitude_mu(amplitude*self.amplitude_scale)
self.set_amplitude_mu(int(amplitude*self.amplitude_scale))

@kernel
def set_frequency_mu(self, frequency: TInt32):
@@ -53,7 +54,7 @@ def set_frequency(self, frequency: TFloat):
:param frequency: DDS frequency in Hz.
"""
self.set_frequency_mu(frequency*self.frequency_scale)
self.set_frequency_mu(int(frequency*self.frequency_scale))

@kernel
def set_phase_mu(self, phase: TInt32):
@@ -69,4 +70,4 @@ def set_phase(self, phase: TFloat):
:param phase: DDS phase relative in turns.
"""
self.set_phase_mu(phase*self.phase_scale)
self.set_phase_mu(int(phase*self.phase_scale))
2 changes: 1 addition & 1 deletion artiq/examples/phaser/device_db.pyon
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@
"type": "local",
"module": "artiq.coredevice.comm_tcp",
"class": "Comm",
"arguments": {"host": "kc705-phaser.lab.m-labs.hk"}
"arguments": {"host": "kc705aux.lab.m-labs.hk"}
},
"core": {
"type": "local",
10 changes: 5 additions & 5 deletions artiq/examples/phaser/repository/sawg.py
Original file line number Diff line number Diff line change
@@ -17,18 +17,18 @@ def run(self):

delay(100*us)
self.sawg0.set_amplitude(.1)
self.sawg1.set_amplitude(-1)
self.sawg1.set_amplitude(-1.)
self.sawg2.set_amplitude(.5)
self.sawg3.set_amplitude(.5)
self.sawg0.set_frequency(1*MHz)
self.sawg1.set_frequency(100*MHz)
self.sawg2.set_frequency(200*MHz)
self.sawg3.set_frequency(200*MHz)
self.sawg0.set_phase(0)
self.sawg1.set_phase(0)
self.sawg2.set_phase(0)
self.sawg0.set_phase(0.)
self.sawg1.set_phase(0.)
self.sawg2.set_phase(0.)
self.sawg3.set_phase(.5)

while True:
for i in range(10):
self.led.pulse(100*ms)
delay(100*ms)
4 changes: 2 additions & 2 deletions artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@ def __init__(self, width, parallelism=4):
self.parallelism = parallelism
self.latency = 1 # will be accumulated

q = PhasedAccu(width, parallelism)
q = PhasedAccu(f_width, parallelism)
self.submodules += q
self.latency += q.latency

@@ -58,7 +58,7 @@ def __init__(self, width, parallelism=4):
c.append(ci)
qoi = getattr(q.o, "z{}".format(i))
self.comb += [
ci.xi.eq(a),
eqh(ci.xi, a),
ci.yi.eq(0),
eqh(ci.zi, qoi),
eqh(self.o[i], ci.xo),
3 changes: 1 addition & 2 deletions artiq/gateware/rtio/phy/sawg.py
Original file line number Diff line number Diff line change
@@ -16,8 +16,7 @@ def __init__(self, *args, **kwargs):
DDSFast_rtio.__init__(self, *args, **kwargs)
self.phys = []
for i in self.i:
rl = rtlink.Interface(rtlink.OInterface(
min(64, len(i.payload))))
rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
self.comb += [
i.stb.eq(rl.o.stb),
rl.o.busy.eq(~i.ack),
14 changes: 9 additions & 5 deletions artiq/runtime/test_mode.c
Original file line number Diff line number Diff line change
@@ -729,10 +729,10 @@ static void dac_test(void)

/* reset */
ad9154_write(AD9154_SPI_INTFCONFA, AD9154_SOFTRESET_SET(1) |
AD9154_LSBFIRST_SET(0) | AD9154_ADDRINC_SET(0) |
AD9154_LSBFIRST_SET(0) | AD9154_ADDRINC_SET(1) |
AD9154_SDOACTIVE_SET(1));
ad9154_write(AD9154_SPI_INTFCONFA,
AD9154_LSBFIRST_SET(0) | AD9154_ADDRINC_SET(0) |
AD9154_LSBFIRST_SET(0) | AD9154_ADDRINC_SET(1) |
AD9154_SDOACTIVE_SET(1));
if (((ad9154_read(AD9154_PRODIDH) << 8) |
ad9154_read(AD9154_PRODIDL)) != 0x9154) {
@@ -925,6 +925,9 @@ static void dac_test(void)
AD9154_SPI_VCO_VARACTOR_REF_TCF_SET(0x7));
ad9154_write(AD9154_VCO_VARACTOR_CTRL_1,
AD9154_SPI_VCO_VARACTOR_REF_SET(0x6));
/* ensure link is txing */
ad9154_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(1));
ad9154_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(0));
ad9154_write(AD9154_EQ_BIAS_REG, AD9154_EQ_BIAS_RESERVED_SET(0x22) |
@@ -937,13 +940,14 @@ static void dac_test(void)
ad9154_write(AD9154_LMFC_VAR_1, 0x0a);
ad9154_write(AD9154_SYNC_ERRWINDOW, 0); /* +- 1/2 DAC clock */
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1));
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(0) |
AD9154_SYNCARM_SET(0));
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1));
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(0));
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(1));
/* ensure sysref pulse */
ad9154_write(AD9154_XBAR_LN_0_1,
AD9154_LOGICAL_LANE0_SRC_SET(7) | AD9154_LOGICAL_LANE1_SRC_SET(6));
ad9154_write(AD9154_XBAR_LN_2_3,