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  • 5 commits
  • 5 files changed
  • 1 contributor

Commits on Oct 2, 2016

  1. ad9514: move setup functions

    jordens committed Oct 2, 2016
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    aab22e3 View commit details
  2. Copy the full SHA
    a79411c View commit details

Commits on Oct 3, 2016

  1. Copy the full SHA
    32be95a View commit details
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    a74ac46 View commit details
  3. phaser: naming cleanup

    jordens committed Oct 3, 2016
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    6e95d7b View commit details
Showing with 336 additions and 311 deletions.
  1. +3 −1 artiq/gateware/targets/kc705.py
  2. +319 −0 artiq/runtime/ad9154.c
  3. +4 −0 artiq/runtime/ad9154.h
  4. +7 −0 artiq/runtime/main.c
  5. +3 −310 artiq/runtime/test_mode.c
4 changes: 3 additions & 1 deletion artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -393,6 +393,8 @@ def __init__(self, cpu_type="or1k", **kwargs):

class _PhaserCRG(Module, AutoCSR):
def __init__(self, platform, rtio_internal_clk):
rtio_internal_clk = ClockSignal("sys4x")

self._clock_sel = CSRStorage()
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
@@ -419,7 +421,7 @@ def __init__(self, platform, rtio_internal_clk):

p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
p_CLKIN1_PERIOD=2.0, p_CLKIN2_PERIOD=2.0,
i_CLKIN1=self.cd_refclk.clk, i_CLKIN2=self.cd_refclk.clk,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.cd_refclk.clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

319 changes: 319 additions & 0 deletions artiq/runtime/ad9154.c
Original file line number Diff line number Diff line change
@@ -54,4 +54,323 @@ uint8_t ad9516_read(uint16_t addr)
return ad9154_spi_data_read_read();
}

int ad9154_init(void)
{
int i;
ad9154_spi_config();

/* reset */
ad9154_write(AD9154_SPI_INTFCONFA, AD9154_SOFTRESET_SET(1) |
AD9154_LSBFIRST_SET(0) | AD9154_SDOACTIVE_SET(1));
ad9154_write(AD9154_SPI_INTFCONFA,
AD9154_LSBFIRST_SET(0) | AD9154_SDOACTIVE_SET(1));
if (((ad9154_read(AD9154_PRODIDH) << 8) |
ad9154_read(AD9154_PRODIDL)) != 0x9154) {
return -1;
}

ad9154_write(AD9154_PWRCNTRL0,
AD9154_PD_DAC0_SET(0) | AD9154_PD_DAC1_SET(0) |
AD9154_PD_DAC2_SET(0) | AD9154_PD_DAC3_SET(0) |
AD9154_PD_BG_SET(0));
ad9154_write(AD9154_TXENMASK1, AD9154_DACA_MASK_SET(0) |
AD9154_DACB_MASK_SET(0)); /* TX not controlled by TXEN pins */
ad9154_write(AD9154_CLKCFG0,
AD9154_REF_CLKDIV_EN_SET(0) | AD9154_RF_SYNC_EN_SET(1) |
AD9154_DUTY_EN_SET(1) | AD9154_PD_CLK_REC_SET(0) |
AD9154_PD_SERDES_PCLK_SET(0) | AD9154_PD_CLK_DIG_SET(0) |
AD9154_PD_CLK23_SET(0) | AD9154_PD_CLK01_SET(0));
ad9154_write(AD9154_DACPLLCNTRL,
AD9154_ENABLE_DACPLL_SET(0) | AD9154_RECAL_DACPLL_SET(0));
ad9154_write(AD9154_SYSREF_ACTRL0, /* jesd204b subclass 1 */
AD9154_HYS_CNTRL1_SET(0) | AD9154_SYSREF_RISE_SET(0) |
AD9154_HYS_ON_SET(0) | AD9154_PD_SYSREF_BUFFER_SET(0));

ad9154_write(AD9154_DEVICE_CONFIG_REG_0, 0x8b); /* magic */
ad9154_write(AD9154_DEVICE_CONFIG_REG_1, 0x01); /* magic */
ad9154_write(AD9154_DEVICE_CONFIG_REG_2, 0x01); /* magic */

ad9154_write(AD9154_SPI_PAGEINDX, 0x3); /* A and B dual */

ad9154_write(AD9154_INTERP_MODE, 3); /* 4x */
ad9154_write(AD9154_MIX_MODE, 0);
ad9154_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)); /* s16 */
ad9154_write(AD9154_DATAPATH_CTRL,
AD9154_I_TO_Q_SET(0) | AD9154_SEL_SIDEBAND_SET(0) |
AD9154_MODULATION_TYPE_SET(0) | AD9154_PHASE_ADJ_ENABLE_SET(0) |
AD9154_DIG_GAIN_ENABLE_SET(0) | AD9154_INVSINC_ENABLE_SET(0));
ad9154_write(AD9154_IDAC_DIG_GAIN0, 0x00);
ad9154_write(AD9154_IDAC_DIG_GAIN1, 0x8);
ad9154_write(AD9154_QDAC_DIG_GAIN0, 0x00);
ad9154_write(AD9154_QDAC_DIG_GAIN1, 0x8);
ad9154_write(AD9154_DC_OFFSET_CTRL, 0);
ad9154_write(AD9154_IPATH_DC_OFFSET_1PART0, 0x00);
ad9154_write(AD9154_IPATH_DC_OFFSET_1PART1, 0x00);
ad9154_write(AD9154_IPATH_DC_OFFSET_2PART, 0x00);
ad9154_write(AD9154_QPATH_DC_OFFSET_1PART0, 0x00);
ad9154_write(AD9154_QPATH_DC_OFFSET_1PART1, 0x00);
ad9154_write(AD9154_QPATH_DC_OFFSET_2PART, 0x00);
ad9154_write(AD9154_PHASE_ADJ0, 0);
ad9154_write(AD9154_PHASE_ADJ1, 0);
ad9154_write(AD9154_GROUP_DLY, AD9154_COARSE_GROUP_DELAY_SET(0x8) |
AD9154_GROUP_DELAY_RESERVED_SET(0x8));
ad9154_write(AD9154_GROUPDELAY_COMP_BYP,
AD9154_GROUPCOMP_BYPQ_SET(1) |
AD9154_GROUPCOMP_BYPI_SET(1));
ad9154_write(AD9154_GROUPDELAY_COMP_I, 0);
ad9154_write(AD9154_GROUPDELAY_COMP_Q, 0);
ad9154_write(AD9154_PDP_AVG_TIME, AD9154_PDP_ENABLE_SET(0));

/* ad9154 mode 2:
* M=4 converters
* L=4 lanes
* S=1 samples/converter and /frame
* F=2 octets/lane and /frame
* K=16 frames/multiframe (or 32)
* HD=0 high density
* N=16 bits/converter
* NB=16 bits/sample
* pclock=250MHz
* fclock=500MHz
* fdata=500MHz
* fline=10GHz
*/

ad9154_write(AD9154_MASTER_PD, 0);
ad9154_write(AD9154_PHY_PD, 0x0f); /* power down lanes 0-3 */
ad9154_write(AD9154_GENERIC_PD,
AD9154_PD_SYNCOUT0B_SET(0) |
AD9154_PD_SYNCOUT1B_SET(1));
ad9154_write(AD9154_GENERAL_JRX_CTRL_0,
AD9154_LINK_EN_SET(0x0) | AD9154_LINK_PAGE_SET(0) |
AD9154_LINK_MODE_SET(0) | AD9154_CHECKSUM_MODE_SET(0));
ad9154_write(AD9154_ILS_DID, 0x00); /* device id */
ad9154_write(AD9154_ILS_BID, 0x00); /* band id */
ad9154_write(AD9154_ILS_LID0, 0x00); /* lane id */
ad9154_write(AD9154_ILS_SCR_L, AD9154_L_1_SET(4 - 1) | AD9154_SCR_SET(1));
ad9154_write(AD9154_ILS_F, 2 - 1);
ad9154_write(AD9154_ILS_K, 16 - 1);
ad9154_write(AD9154_ILS_M, 4 - 1);
ad9154_write(AD9154_ILS_CS_N, AD9154_N_1_SET(16 - 1) | AD9154_CS_SET(0));
ad9154_write(AD9154_ILS_NP, AD9154_NP_1_SET(16 - 1) |
AD9154_SUBCLASSV_SET(1));
ad9154_write(AD9154_ILS_S, AD9154_S_1_SET(1 - 1) | AD9154_JESDV_SET(1));
ad9154_write(AD9154_ILS_HD_CF, AD9154_HD_SET(0) | AD9154_CF_SET(0));
ad9154_write(AD9154_ILS_CHECKSUM,
0x00 + 0x00 + 0x00 + 1 + (4 - 1) + /* DID BID LID SCR L */
(2 - 1) + (16 - 1) + (4 - 1) + (16 - 1) + /* F K M N */
1 + (16 - 1) + 1 + (1 - 1) + 0 /* SUBC NP JESDV S HD */);
ad9154_write(AD9154_LANEDESKEW, 0xf0);
for(i=0; i<8; i++) {
ad9154_write(AD9154_BADDISPARITY, AD9154_RST_IRQ_DIS_SET(0) |
AD9154_DISABLE_ERR_CNTR_DIS_SET(0) |
AD9154_RST_ERR_CNTR_DIS_SET(1) | AD9154_LANE_ADDR_DIS_SET(i));
ad9154_write(AD9154_BADDISPARITY, AD9154_RST_IRQ_DIS_SET(0) |
AD9154_DISABLE_ERR_CNTR_DIS_SET(0) |
AD9154_RST_ERR_CNTR_DIS_SET(0) | AD9154_LANE_ADDR_DIS_SET(i));
ad9154_write(AD9154_NIT_W, AD9154_RST_IRQ_NIT_SET(0) |
AD9154_DISABLE_ERR_CNTR_NIT_SET(0) |
AD9154_RST_ERR_CNTR_NIT_SET(1) | AD9154_LANE_ADDR_NIT_SET(i));
ad9154_write(AD9154_NIT_W, AD9154_RST_IRQ_NIT_SET(0) |
AD9154_DISABLE_ERR_CNTR_NIT_SET(0) |
AD9154_RST_ERR_CNTR_NIT_SET(0) | AD9154_LANE_ADDR_NIT_SET(i));
ad9154_write(AD9154_UNEXPECTEDCONTROL_W, AD9154_RST_IRQ_UCC_SET(0) |
AD9154_DISABLE_ERR_CNTR_UCC_SET(0) |
AD9154_RST_ERR_CNTR_UCC_SET(1) | AD9154_LANE_ADDR_UCC_SET(i));
ad9154_write(AD9154_BADDISPARITY, AD9154_RST_IRQ_UCC_SET(0) |
AD9154_DISABLE_ERR_CNTR_UCC_SET(0) |
AD9154_RST_ERR_CNTR_UCC_SET(0) | AD9154_LANE_ADDR_UCC_SET(i));
}
ad9154_write(AD9154_CTRLREG1, 2); /* F */
ad9154_write(AD9154_CTRLREG2, AD9154_ILAS_MODE_SET(0) |
AD9154_THRESHOLD_MASK_EN_SET(0));
ad9154_write(AD9154_KVAL, 1); /* 4*K multiframes during ILAS */
ad9154_write(AD9154_LANEENABLE, 0xf0);

ad9154_write(AD9154_TERM_BLK1_CTRLREG0, 1);
ad9154_write(AD9154_TERM_BLK2_CTRLREG0, 1);
ad9154_write(AD9154_SERDES_SPI_REG, 1);
ad9154_write(AD9154_CDR_OPERATING_MODE_REG_0,
AD9154_CDR_OVERSAMP_SET(0) | AD9154_CDR_RESERVED_SET(0x2) |
AD9154_ENHALFRATE_SET(1));
ad9154_write(AD9154_CDR_RESET, 0);
ad9154_write(AD9154_CDR_RESET, 1);
ad9154_write(AD9154_REF_CLK_DIVIDER_LDO,
AD9154_SPI_CDR_OVERSAMP_SET(0x0) |
AD9154_SPI_LDO_BYPASS_FILT_SET(1) |
AD9154_SPI_LDO_REF_SEL_SET(0));
ad9154_write(AD9154_LDO_FILTER_1, 0x62); /* magic */
ad9154_write(AD9154_LDO_FILTER_2, 0xc9); /* magic */
ad9154_write(AD9154_LDO_FILTER_3, 0x0e); /* magic */
ad9154_write(AD9154_CP_CURRENT_SPI,
AD9154_SPI_CP_CURRENT_SET(0x12) |
AD9154_SPI_SERDES_LOGEN_POWER_MODE_SET(0));
ad9154_write(AD9154_VCO_LDO, 0x7b); /* magic */
ad9154_write(AD9154_PLL_RD_REG,
AD9154_SPI_SERDES_LOGEN_PD_CORE_SET(0) |
AD9154_SPI_SERDES_LDO_PD_SET(0) | AD9154_SPI_SYN_PD_SET(0) |
AD9154_SPI_VCO_PD_ALC_SET(0) | AD9154_SPI_VCO_PD_PTAT_SET(0) |
AD9154_SPI_VCO_PD_SET(0));
ad9154_write(AD9154_ALC_VARACTOR,
AD9154_SPI_VCO_VARACTOR_SET(0x9) |
AD9154_SPI_INIT_ALC_VALUE_SET(0x8));
ad9154_write(AD9154_VCO_OUTPUT,
AD9154_SPI_VCO_OUTPUT_LEVEL_SET(0xc) |
AD9154_SPI_VCO_OUTPUT_RESERVED_SET(0x4));
ad9154_write(AD9154_CP_CONFIG,
AD9154_SPI_CP_TEST_SET(0) |
AD9154_SPI_CP_CAL_EN_SET(1) |
AD9154_SPI_CP_FORCE_CALBITS_SET(0) |
AD9154_SPI_CP_OFFSET_OFF_SET(0) |
AD9154_SPI_CP_ENABLE_MACHINE_SET(1) |
AD9154_SPI_CP_DITHER_MODE_SET(0) |
AD9154_SPI_CP_HALF_VCO_CAL_CLK_SET(0));
ad9154_write(AD9154_VCO_BIAS_1,
AD9154_SPI_VCO_BIAS_REF_SET(0x3) |
AD9154_SPI_VCO_BIAS_TCF_SET(0x3));
ad9154_write(AD9154_VCO_BIAS_2,
AD9154_SPI_PRESCALE_BIAS_SET(0x1) |
AD9154_SPI_LAST_ALC_EN_SET(1) |
AD9154_SPI_PRESCALE_BYPASS_R_SET(0x1) |
AD9154_SPI_VCO_COMP_BYPASS_BIASR_SET(0) |
AD9154_SPI_VCO_BYPASS_DAC_R_SET(0));
ad9154_write(AD9154_VCO_PD_OVERRIDES,
AD9154_SPI_VCO_PD_OVERRIDE_VCO_BUF_SET(0) |
AD9154_SPI_VCO_PD_OVERRIDE_CAL_TCF_SET(1) |
AD9154_SPI_VCO_PD_OVERRIDE_VAR_REF_TCF_SET(0) |
AD9154_SPI_VCO_PD_OVERRIDE_VAR_REF_SET(0));
ad9154_write(AD9154_VCO_CAL,
AD9154_SPI_FB_CLOCK_ADV_SET(0x2) |
AD9154_SPI_VCO_CAL_COUNT_SET(0x3) |
AD9154_SPI_VCO_CAL_ALC_WAIT_SET(0) |
AD9154_SPI_VCO_CAL_EN_SET(1));
ad9154_write(AD9154_CP_LEVEL_DETECT,
AD9154_SPI_CP_LEVEL_THRESHOLD_HIGH_SET(0x2) |
AD9154_SPI_CP_LEVEL_THRESHOLD_LOW_SET(0x5) |
AD9154_SPI_CP_LEVEL_DET_PD_SET(0));
ad9154_write(AD9154_VCO_VARACTOR_CTRL_0,
AD9154_SPI_VCO_VARACTOR_OFFSET_SET(0xe) |
AD9154_SPI_VCO_VARACTOR_REF_TCF_SET(0x7));
ad9154_write(AD9154_VCO_VARACTOR_CTRL_1,
AD9154_SPI_VCO_VARACTOR_REF_SET(0x6));
/* ensure link is txing */
ad9154_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(1));
ad9154_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(0));
ad9154_write(AD9154_EQ_BIAS_REG, AD9154_EQ_BIAS_RESERVED_SET(0x22) |
AD9154_EQ_POWER_MODE_SET(1));

ad9154_write(AD9154_GENERAL_JRX_CTRL_1, 1); /* subclass 1 */
ad9154_write(AD9154_LMFC_DELAY_0, 0);
ad9154_write(AD9154_LMFC_DELAY_1, 0);
ad9154_write(AD9154_LMFC_VAR_0, 0x0a); /* receive buffer delay */
ad9154_write(AD9154_LMFC_VAR_1, 0x0a);
ad9154_write(AD9154_SYNC_ERRWINDOW, 0); /* +- 1/2 DAC clock */
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(0) |
AD9154_SYNCARM_SET(0));
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(0));
ad9154_write(AD9154_SYNC_CONTROL,
AD9154_SYNCMODE_SET(1) | AD9154_SYNCENABLE_SET(1) |
AD9154_SYNCARM_SET(1));
ad9154_write(AD9154_XBAR_LN_0_1,
AD9154_LOGICAL_LANE0_SRC_SET(7) | AD9154_LOGICAL_LANE1_SRC_SET(6));
ad9154_write(AD9154_XBAR_LN_2_3,
AD9154_LOGICAL_LANE2_SRC_SET(5) | AD9154_LOGICAL_LANE3_SRC_SET(4));
ad9154_write(AD9154_XBAR_LN_4_5,
AD9154_LOGICAL_LANE4_SRC_SET(0) | AD9154_LOGICAL_LANE5_SRC_SET(0));
ad9154_write(AD9154_XBAR_LN_6_7,
AD9154_LOGICAL_LANE6_SRC_SET(0) | AD9154_LOGICAL_LANE7_SRC_SET(0));
ad9154_write(AD9154_JESD_BIT_INVERSE_CTRL, 0x00);
ad9154_write(AD9154_GENERAL_JRX_CTRL_0,
AD9154_LINK_EN_SET(0x1) | AD9154_LINK_PAGE_SET(0) |
AD9154_LINK_MODE_SET(0) | AD9154_CHECKSUM_MODE_SET(0));

return 0;
}

int ad9516_init(void)
{
ad9154_spi_config();

/* reset */
ad9516_write(AD9516_SERIAL_PORT_CONFIGURATION,
AD9516_SOFT_RESET | AD9516_SOFT_RESET_MIRRORED |
AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED |
AD9516_SDO_ACTIVE | AD9516_SDO_ACTIVE_MIRRORED);
ad9516_write(AD9516_SERIAL_PORT_CONFIGURATION,
AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED |
AD9516_SDO_ACTIVE | AD9516_SDO_ACTIVE_MIRRORED);
if (ad9516_read(AD9516_PART_ID) != 0x41) {
return -1;
}

/* ad9154 mode 2:
* M=4 converters
* L=4 lanes
* S=1 samples/converter and /frame
* F=2 octets/lane and /frame
* K=16 frames/multiframe (or 32)
* HD=0 high density
* N=16 bits/converter
* NB=16 bits/sample
* pclock=250MHz
* fdata=500MHz
* fline=10GHz
* deviceclock_fpga=500MHz
* deviceclock_dac=2000MHz
*/

/* clk=2000MHz */

/* use clk input, dclk=clk/4 */
ad9516_write(AD9516_PFD_AND_CHARGE_PUMP, 1*AD9516_PLL_POWER_DOWN |
0*AD9516_CHARGE_PUMP_MODE);
ad9516_write(AD9516_VCO_DIVIDER, 2);
ad9516_write(AD9516_INPUT_CLKS, 0*AD9516_SELECT_VCO_OR_CLK |
0*AD9516_BYPASS_VCO_DIVIDER);

ad9516_write(AD9516_OUT0, 2*AD9516_OUT0_POWER_DOWN);
ad9516_write(AD9516_OUT2, 2*AD9516_OUT2_POWER_DOWN);
ad9516_write(AD9516_OUT3, 2*AD9516_OUT3_POWER_DOWN);
ad9516_write(AD9516_OUT4, 2*AD9516_OUT4_POWER_DOWN);
ad9516_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN);
ad9516_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN);

/* DAC deviceclk, clk/1 */
ad9516_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT);
ad9516_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE);

/* FPGA deviceclk, dclk/1 */
ad9516_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_1 |
AD9516_DIVIDER_4_BYPASS_2);
ad9516_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF);
ad9516_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
0*AD9516_OUT9_SELECT_LVDS_CMOS);

/* sysref f_data*S/(K*F), dclk/32 */
ad9516_write(AD9516_DIVIDER_3_0, 15*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
15*AD9516_DIVIDER_3_LOW_CYCLES_1);
ad9516_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1 |
0*AD9516_DIVIDER_3_PHASE_OFFSET_2);
ad9516_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC |
0*AD9516_DIVIDER_3_BYPASS_1 | 1*AD9516_DIVIDER_3_BYPASS_2);
ad9516_write(AD9516_DIVIDER_3_4, 1*AD9516_DIVIDER_3_DCCOFF);
ad9516_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT |
2*AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY |
0*AD9516_OUT6_SELECT_LVDS_CMOS);
ad9516_write(AD9516_OUT7, 1*AD9516_OUT7_LVDS_OUTPUT_CURRENT |
2*AD9516_OUT7_LVDS_CMOS_OUTPUT_POLARITY |
0*AD9516_OUT7_SELECT_LVDS_CMOS);

ad9516_write(AD9516_UPDATE_ALL_REGISTERS, 1);

return 0;
}

#endif
4 changes: 4 additions & 0 deletions artiq/runtime/ad9154.h
Original file line number Diff line number Diff line change
@@ -10,8 +10,12 @@ void ad9154_spi_config(void);
void ad9154_write(uint16_t addr, uint8_t data);
uint8_t ad9154_read(uint16_t addr);

int ad9154_init(void);

void ad9516_write(uint16_t addr, uint8_t data);
uint8_t ad9516_read(uint16_t addr);

int ad9516_init(void);

#endif
#endif
7 changes: 7 additions & 0 deletions artiq/runtime/main.c
Original file line number Diff line number Diff line change
@@ -34,6 +34,7 @@
#include "session.h"
#include "analyzer.h"
#include "moninj.h"
#include "ad9154.h"

u32_t sys_now(void)
{
@@ -278,6 +279,12 @@ int main(void)

alloc_give(&_fheap, &_eheap - &_fheap);
clock_init();
#ifdef CONFIG_AD9154_DAC_CS
if (ad9516_init())
puts("AD9516 init failed");
if (ad9154_init())
puts("AD9154 init failed");
#endif
rtiocrg_init();
puts("Press 't' to enter test mode...");
blink_led();
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