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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: e998a980b385
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Oct 7, 2016

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Showing with 9 additions and 5 deletions.
  1. +1 −1 artiq/examples/phaser/repository/dac_setup.py
  2. +7 −3 artiq/examples/phaser/startup_kernel.py
  3. +1 −1 artiq/gateware/targets/kc705.py
2 changes: 1 addition & 1 deletion artiq/examples/phaser/repository/dac_setup.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@
cs=1, #
)
jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
jesd_checksum = jesd_settings.get_configuration_data()[-1]
jesd_checksum = jesd_settings.get_configuration_checksum()
# external clk=2000MHz
# pclock=250MHz
# deviceclock_fpga=500MHz
10 changes: 7 additions & 3 deletions artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,5 @@
from math import ceil

from artiq.experiment import *
from artiq.coredevice.ad9516_reg import *

@@ -47,9 +49,11 @@ def clock_setup(self):
self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)

# FPGA deviceclk, dclk/1
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_1 |
AD9516_DIVIDER_4_BYPASS_2)
# FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
self.ad9154.clock_write(AD9516_DIVIDER_0_0,
(ceil(4/2)-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)
self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -460,7 +460,7 @@ def __init__(self, platform, rtio_crg):
ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
jesd_linerate = 5e9
jesd_refclk_freq = 500e6
jesd_refclk_freq = 125e6
rtio_freq = 125*1000*1000
jesd_phys = [JESD204BPhyTX(
rtio_crg.refclk, jesd_refclk_freq,