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phaser: fix fpga deviceclock divider
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jordens committed Oct 7, 2016
1 parent 9b860b2 commit cfd2fe8
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -49,7 +49,7 @@ def clock_setup(self):

# FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
self.ad9154.clock_write(AD9516_DIVIDER_0_0,
self.ad9154.clock_write(AD9516_DIVIDER_4_0,
(4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)

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