Skip to content

Commit

Permalink
phaser: also adapt rtio_crg
Browse files Browse the repository at this point in the history
jordens committed Oct 7, 2016
1 parent e998a98 commit 09434ec
Showing 1 changed file with 4 additions and 6 deletions.
10 changes: 4 additions & 6 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -392,16 +392,14 @@ def __init__(self, cpu_type="or1k", **kwargs):

class _PhaserCRG(Module, AutoCSR):
def __init__(self, platform, rtio_internal_clk):
rtio_internal_clk = ClockSignal("sys4x")

self._clock_sel = CSRStorage()
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)

refclk_pads = platform.request("ad9154_refclk")
platform.add_period_constraint(refclk_pads.p, 2.)
platform.add_period_constraint(refclk_pads.p, 5.)
self.refclk = Signal()
self.clock_domains.cd_refclk = ClockDomain()
self.specials += [
@@ -419,12 +417,12 @@ def __init__(self, platform, rtio_internal_clk):

p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
p_CLKIN1_PERIOD=2.0, p_CLKIN2_PERIOD=2.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.cd_refclk.clk,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.refclk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

# VCO @ 1GHz when using 500MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=4,
# VCO @ 1GHz when using 125MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,

0 comments on commit 09434ec

Please sign in to comment.