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phaser: fix rtio pll inputs
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jordens committed Oct 7, 2016
1 parent c846e75 commit 9b860b2
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -416,8 +416,8 @@ def __init__(self, platform, rtio_internal_clk):
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,

p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
p_CLKIN1_PERIOD=2.0, p_CLKIN2_PERIOD=2.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.refclk,
p_CLKIN1_PERIOD=5.0, p_CLKIN2_PERIOD=5.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.cd_refclk.clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,

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