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phaser: fix startup_kernel/ceil
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jordens committed Oct 7, 2016
1 parent 09434ec commit c846e75
Showing 1 changed file with 1 addition and 3 deletions.
4 changes: 1 addition & 3 deletions artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,3 @@
from math import ceil

from artiq.experiment import *
from artiq.coredevice.ad9516_reg import *

@@ -52,7 +50,7 @@ def clock_setup(self):
# FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
self.ad9154.clock_write(AD9516_DIVIDER_0_0,
(ceil(4/2)-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)
self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |

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