Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: d2f776b0d0cf^
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: e981b235486f
Choose a head ref
  • 2 commits
  • 5 files changed
  • 1 contributor

Commits on Oct 24, 2016

  1. phaser: add more tools

    jordens committed Oct 24, 2016
    Copy the full SHA
    d2f776b View commit details
  2. phaser: use misoc cordic

    jordens committed Oct 24, 2016
    Copy the full SHA
    e981b23 View commit details
Showing with 122 additions and 359 deletions.
  1. +0 −358 artiq/gateware/dsp/cordic.py
  2. +1 −1 artiq/gateware/dsp/sawg.py
  3. +46 −0 artiq/gateware/dsp/spline.py
  4. +44 −0 artiq/gateware/dsp/tools.py
  5. +31 −0 artiq/test/gateware/test_spline.py
358 changes: 0 additions & 358 deletions artiq/gateware/dsp/cordic.py

This file was deleted.

2 changes: 1 addition & 1 deletion artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from migen import *
from misoc.interconnect.stream import Endpoint

from .cordic import Cordic
from misoc.cores.cordic import Cordic
from .accu import PhasedAccu
from .tools import eqh

46 changes: 46 additions & 0 deletions artiq/gateware/dsp/spline.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
from migen import *
from misoc.interconnect.stream import Endpoint


class Spline(Module):
def __init__(self, order, width, step=1, time_width=None):
if not (step == 1 or order <= 2):
raise ValueError("For non-linear splines, "
"`step` needs to be one.")
layout = [("a{}".format(i), (width, True)) for i in range(order)]
self.i = Endpoint(layout)
self.o = Endpoint(layout)
self.latency = 1

###

o = self.o.payload.flatten()

self.comb += self.i.ack.eq(~self.o.stb | self.o.ack)
self.sync += [
If(self.o.ack,
self.o.stb.eq(0),
),
If(self.i.ack,
self.o.stb.eq(1),
[o[i].eq(o[i] + (o[i + 1] << log2_int(step)))
for i in range(order - 1)],
If(self.i.stb,
self.o.payload.eq(self.i.payload),
),
),
]

def tri(self, time_width):
layout = [(name, (length - i*time_width, signed))
for i, (name, (length, signed), dir) in
enumerate(self.i.payload.layout[::-1])]
layout.reverse()
i = Endpoint(layout)
self.comb += [
self.i.stb.eq(i.stb),
i.ack.eq(self.i.ack),
[i0[-len(i1):].eq(i1) for i0, i1 in
zip(self.i.payload.flatten(), i.payload.flatten())]
]
return i
44 changes: 44 additions & 0 deletions artiq/gateware/dsp/tools.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,6 @@
from operator import add
from functools import reduce

from migen import *


@@ -27,10 +30,51 @@ def xfer(dut, **kw):
ep.remove(e)


class Delay(Module):
def __init__(self, i, delay, o=None):
if isinstance(i, (int, tuple)):
z = [Signal(i) for j in range(delay + 1)]
elif isinstance(i, list):
z = [Record(i) for j in range(delay + 1)]
elif isinstance(i, Record):
z = [Record(i.layout) for j in range(delay + 1)]
else:
z = [Signal.like(i) for j in range(delay + 1)]
self.i = z[0]
self.o = z[-1]
if not isinstance(i, (int, list, tuple)):
self.comb += self.i.eq(i)
if o is not None:
self.comb += o.eq(self.o)
self.latency = delay
self.sync += [z[j + 1].eq(z[j]) for j in range(delay)]


def eqh(a, b):
return a[-len(b):].eq(b[-len(a):])


class SatAddMixin:
def sat_add(self, a):
a = list(a)
# assert all(value_bits_sign(ai)[1] for ai in a)
n = max(len(ai) for ai in a)
o = log2_int(len(a), need_pow2=False)
s = Signal((n + o, True))
s0 = Signal((n, True))
z = Signal((1, True))
self.comb += [
s.eq(reduce(add, a, z)),
s0[-1].eq(s[-1]),
If(s[-o-1:] == Replicate(s[-1], o + 1),
s0[:-1].eq(s[:n-1]),
).Else(
s0[:-1].eq(Replicate(~s[-1], n - 1)),
)
]
return s0


def szip(*iters):
active = {it: None for it in iters}
while active:
31 changes: 31 additions & 0 deletions artiq/test/gateware/test_spline.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
import numpy as np

from migen import *
from migen.fhdl.verilog import convert

from artiq.gateware.dsp.spline import Spline
from artiq.gateware.dsp.tools import xfer


def _test_gen_spline(dut, o):
yield dut.o.ack.eq(1)
yield from xfer(dut, i=dict(a0=0, a1=1, a2=2))
for i in range(20):
yield
o.append((yield dut.o.a0))


def _test_spline():
dut = Spline(order=3, width=16, step=1)

if False:
print(convert(dut))
else:
o = []
run_simulation(dut, _test_gen_spline(dut, o), vcd_name="spline.vcd")
o = np.array(o)
print(o)


if __name__ == "__main__":
_test_spline()