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phaser: work around for unreliable transciever init
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jordens committed Oct 16, 2016
1 parent 0259c80 commit 6a683c7
Showing 1 changed file with 14 additions and 0 deletions.
14 changes: 14 additions & 0 deletions artiq/examples/phaser/repository/dac_setup.py
Original file line number Diff line number Diff line change
@@ -34,6 +34,19 @@ def build(self):

@kernel
def run(self):
# TODO; remove when
# https://github.com/m-labs/jesd204b/issues/6
# is resolved
for i in range(99):
try:
self.cfg()
return
except:
pass
self.cfg()

@kernel
def cfg(self):
self.core.reset()
self.ad9154.jesd_enable(0)
self.ad9154.jesd_prbs(0)
@@ -48,6 +61,7 @@ def run(self):
self.monitor()
while not self.ad9154.jesd_ready():
pass
self.busywait_us(10000)
if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
raise ValueError("bad CODEGRPSYNCFLG")
self.core.break_realtime()

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