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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 3b1d5d7eb63f
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Oct 11, 2016

  1. Copy the full SHA
    f515c11 View commit details

Commits on Oct 12, 2016

  1. phaser: support core stpl

    jordens committed Oct 12, 2016
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    1117fe1 View commit details
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    3b1d5d7 View commit details
Showing with 36 additions and 14 deletions.
  1. +9 −0 artiq/coredevice/ad9154.py
  2. +18 −3 artiq/examples/phaser/repository/dac_setup.py
  3. +2 −11 artiq/gateware/targets/kc705.py
  4. +5 −0 artiq/runtime/ad9154.c
  5. +1 −0 artiq/runtime/ad9154.h
  6. +1 −0 artiq/runtime/ksupport.c
9 changes: 9 additions & 0 deletions artiq/coredevice/ad9154.py
Original file line number Diff line number Diff line change
@@ -42,6 +42,11 @@ def ad9154_jesd_prbs(prbs: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")


@syscall(flags={"nounwind", "nowrite"})
def ad9154_jesd_stpl(prbs: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")


class AD9154:
"""AD9154-FMC-EBZ SPI support
@@ -95,3 +100,7 @@ def jesd_ready(self):
@kernel
def jesd_prbs(self, prbs):
ad9154_jesd_prbs(prbs)

@kernel
def jesd_stpl(self, enable):
ad9154_jesd_stpl(enable)
21 changes: 18 additions & 3 deletions artiq/examples/phaser/repository/dac_setup.py
Original file line number Diff line number Diff line change
@@ -30,6 +30,7 @@ def build(self):
self.setattr_device("core")
self.setattr_device("led")
self.setattr_device("ad9154")
self.setattr_device("sync")

@kernel
def run(self):
@@ -38,10 +39,21 @@ def run(self):
self.ad9154.jesd_prbs(0)
self.ad9154.init()
self.dac_setup()
self.busywait_us(200000)
self.ad9154.jesd_enable(1)
while not self.ad9154.jesd_ready():
pass
if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
raise ValueError("no CODEGRPSYNCFLG")
self.core.break_realtime()
if not self.sync.sample_get_nonrt():
pass #raise ValueError("SYNC still low")
if self.ad9154.dac_read(AD9154_FRAMESYNCFLG) != 0x0f:
raise ValueError("no FRAMESYNCFLG")
if self.ad9154.dac_read(AD9154_GOODCHKSUMFLG) != 0x0f:
raise ValueError("no GOODCHECKSUMFLG")
if self.ad9154.dac_read(AD9154_INITLANESYNCFLG) != 0x0f:
raise ValueError("no INITLANESYNCFLG")
self.monitor()

@kernel
def busywait_us(self, t):
@@ -241,6 +253,9 @@ def dac_setup(self):
# AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(1))
self.ad9154.dac_write(AD9154_SERDESPLL_ENABLE_CNTRL,
AD9154_ENABLE_SERDESPLL_SET(1) | AD9154_RECAL_SERDESPLL_SET(0))
while not AD9154_SERDES_PLL_LOCK_RB_GET(self.ad9154.dac_read(AD9154_PLL_STATUS)):
pass

self.ad9154.dac_write(AD9154_EQ_BIAS_REG, AD9154_EQ_BIAS_RESERVED_SET(0x22) |
AD9154_EQ_POWER_MODE_SET(1))

@@ -279,8 +294,8 @@ def dac_setup(self):
AD9154_LINK_EN_SET(0x1) | AD9154_LINK_PAGE_SET(0) |
AD9154_LINK_MODE_SET(0) | AD9154_CHECKSUM_MODE_SET(0))

self.busywait_us(1000)

@kernel
def monitor(self):
self.ad9154.dac_write(AD9154_IRQ_STATUS0, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS1, 0x00)
self.ad9154.dac_write(AD9154_IRQ_STATUS2, 0x00)
13 changes: 2 additions & 11 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -402,7 +402,7 @@ def __init__(self, platform, rtio_internal_clk):
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)

refclk_pads = platform.request("ad9154_refclk")
platform.add_period_constraint(refclk_pads.p, 5.)
platform.add_period_constraint(refclk_pads.p, 8.)
self.refclk = Signal()
self.clock_domains.cd_refclk = ClockDomain()
self.specials += [
@@ -419,7 +419,7 @@ def __init__(self, platform, rtio_internal_clk):
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,

p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
p_CLKIN1_PERIOD=5.0, p_CLKIN2_PERIOD=5.0,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
i_CLKIN1=rtio_internal_clk, i_CLKIN2=self.cd_refclk.clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,
@@ -544,15 +544,6 @@ def __init__(self, cpu_type="or1k", **kwargs):
# while at 5 GBps, take every second sample... FIXME
self.comb += conv.eq(Cat(ch.o[::2]))

if False:
# short transport layer test pattern
self.comb += [
self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123),
self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567),
self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab),
self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef)
]

self.comb += jesd_sync.eq(self.ad9154.jesd_sync)


5 changes: 5 additions & 0 deletions artiq/runtime/ad9154.c
Original file line number Diff line number Diff line change
@@ -69,4 +69,9 @@ void ad9154_jesd_prbs(int p)
ad9154_jesd_control_prbs_config_write(p);
}

void ad9154_jesd_stpl(int en)
{
ad9154_jesd_control_stpl_enable_write(en);
}

#endif /* CONFIG_AD9154_DAC_CS */
1 change: 1 addition & 0 deletions artiq/runtime/ad9154.h
Original file line number Diff line number Diff line change
@@ -13,6 +13,7 @@ uint8_t ad9516_read(uint16_t addr);
void ad9154_jesd_enable(int en);
int ad9154_jesd_ready(void);
void ad9154_jesd_prbs(int p);
void ad9154_jesd_stpl(int en);

#endif
#endif
1 change: 1 addition & 0 deletions artiq/runtime/ksupport.c
Original file line number Diff line number Diff line change
@@ -147,6 +147,7 @@ static const struct symbol runtime_exports[] = {
{"ad9154_jesd_enable", &ad9154_jesd_enable},
{"ad9154_jesd_ready", &ad9154_jesd_ready},
{"ad9154_jesd_prbs", &ad9154_jesd_prbs},
{"ad9154_jesd_stpl", &ad9154_jesd_stpl},
#endif

/* end */