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base repository: m-labs/artiq
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head repository: m-labs/artiq
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  • 5 commits
  • 5 files changed
  • 1 contributor

Commits on Oct 12, 2016

  1. phaser: 500 MHz dacclock

    jordens committed Oct 12, 2016
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    5f737be View commit details
  2. phaser: update stpl

    jordens committed Oct 12, 2016
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    466d1e8 View commit details
  3. phaser: tweak dac_setup

    jordens committed Oct 12, 2016
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    3f1d96b View commit details
  4. phaser: slow down spi a bit

    jordens committed Oct 12, 2016
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    4376ef5 View commit details
  5. Copy the full SHA
    9644a3a View commit details
2 changes: 1 addition & 1 deletion artiq/coredevice/ad9154_reg.py
Original file line number Diff line number Diff line change
@@ -748,7 +748,7 @@ def AD9154_GROUPCOMP_BYPI_GET(x: TInt32) -> TInt32:
return (x >> 1) & 0x1


AD9154_MIX_MODE = 0x047
AD9154_MIX_MODE = 0x04a

AD9154_NCOALIGN_MODE = 0x050
# default: 0x00, access: R/W
18 changes: 10 additions & 8 deletions artiq/examples/phaser/repository/dac_setup.py
Original file line number Diff line number Diff line change
@@ -20,9 +20,9 @@
jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
jesd_checksum = jesd_settings.get_configuration_checksum()
# external clk=2000MHz
# pclock=250MHz
# deviceclock_fpga=500MHz
# deviceclock_dac=2000MHz
# pclock=125MHz
# deviceclock_fpga=125MHz
# deviceclock_dac=500MHz


class DACSetup(EnvExperiment):
@@ -37,11 +37,14 @@ def run(self):
self.core.break_realtime()
self.ad9154.jesd_enable(0)
self.ad9154.jesd_prbs(0)
self.busywait_us(10000)
self.ad9154.init()
self.dac_setup()
self.busywait_us(10000)
self.ad9154.jesd_enable(1)
while not self.ad9154.jesd_ready():
pass
self.monitor()
if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
raise ValueError("no CODEGRPSYNCFLG")
self.core.break_realtime()
@@ -53,7 +56,6 @@ def run(self):
raise ValueError("no GOODCHECKSUMFLG")
if self.ad9154.dac_read(AD9154_INITLANESYNCFLG) != 0x0f:
raise ValueError("no INITLANESYNCFLG")
self.monitor()

@kernel
def busywait_us(self, t):
@@ -98,13 +100,13 @@ def dac_setup(self):

self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual

self.ad9154.dac_write(AD9154_INTERP_MODE, 4) # 8x
self.ad9154.dac_write(AD9154_INTERP_MODE, 1) # 2x
self.ad9154.dac_write(AD9154_MIX_MODE, 0)
self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
AD9154_I_TO_Q_SET(0) | AD9154_SEL_SIDEBAND_SET(0) |
AD9154_MODULATION_TYPE_SET(0) | AD9154_PHASE_ADJ_ENABLE_SET(0) |
AD9154_DIG_GAIN_ENABLE_SET(0) | AD9154_INVSINC_ENABLE_SET(0))
AD9154_DIG_GAIN_ENABLE_SET(1) | AD9154_INVSINC_ENABLE_SET(0))
self.ad9154.dac_write(AD9154_IDAC_DIG_GAIN0, 0x00)
self.ad9154.dac_write(AD9154_IDAC_DIG_GAIN1, 0x8)
self.ad9154.dac_write(AD9154_QDAC_DIG_GAIN0, 0x00)
@@ -179,8 +181,8 @@ def dac_setup(self):
self.ad9154.dac_write(AD9154_CTRLREG1, jesd_settings.transport.f)
self.ad9154.dac_write(AD9154_CTRLREG2, AD9154_ILAS_MODE_SET(0) |
AD9154_THRESHOLD_MASK_EN_SET(0))
self.ad9154.dac_write(AD9154_KVAL, 1) # *4*K multiframes during ILAS
self.ad9154.dac_write(AD9154_LANEENABLE, 0x0f)
self.ad9154.dac_write(AD9154_KVAL, 1) # *4*K multiframes during ILAS
self.ad9154.dac_write(AD9154_LANEENABLE, 0x0f) # CGS _after_ this

self.ad9154.dac_write(AD9154_TERM_BLK1_CTRLREG0, 1)
self.ad9154.dac_write(AD9154_TERM_BLK2_CTRLREG0, 1)
71 changes: 38 additions & 33 deletions artiq/examples/phaser/repository/test_ad9154_stpl.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
import time
from jesd204b.transport import seed_to_data

from artiq.coredevice.ad9154_reg import *
from artiq.experiment import *
@@ -10,36 +10,41 @@ def build(self):
self.setattr_device("ad9154")

def run(self):
self.stpl()

def stpl(self):
self.ad9154.jesd_stpl(0)
# short transport layer test
for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]):
# select dac
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(0) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# set expected value
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
# enable stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(1) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# release reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)))
for i in range(4):
data = seed_to_data(i << 8, True)
fail = self.stpl(i, data)
print("channel", i, "FAIL" if fail else "PASS")
self.ad9154.jesd_stpl(0)

@kernel
def stpl(self, i, data):
# select dac
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(0) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# set expected value
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
# enable stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(1) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# release reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
return self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)
12 changes: 8 additions & 4 deletions artiq/examples/phaser/startup_kernel.py
Original file line number Diff line number Diff line change
@@ -42,10 +42,14 @@ def clock_setup(self):
self.ad9154.clock_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN)
self.ad9154.clock_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN)

# DAC deviceclk, clk/1
self.ad9154.clock_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT)
self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
# DAC deviceclk, dclk/1
self.ad9154.clock_write(AD9516_DIVIDER_0_1, AD9516_DIVIDER_0_BYPASS)
self.ad9154.clock_write(AD9516_DIVIDER_0_2,
0*AD9516_DIVIDER_0_DIRECT_TO_OUTPUT |
0*AD9516_DIVIDER_0_DCCOFF)
self.ad9154.clock_write(AD9516_OUT1,
0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)

# FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
4 changes: 2 additions & 2 deletions artiq/runtime/ad9154.c
Original file line number Diff line number Diff line change
@@ -16,8 +16,8 @@ void ad9154_init(void)
ad9154_spi_clk_phase_write(0);
ad9154_spi_lsb_first_write(0);
ad9154_spi_half_duplex_write(0);
ad9154_spi_clk_div_write_write(11);
ad9154_spi_clk_div_read_write(11);
ad9154_spi_clk_div_write_write(16);
ad9154_spi_clk_div_read_write(16);
ad9154_spi_xfer_len_write_write(24);
ad9154_spi_xfer_len_read_write(0);
ad9154_spi_cs_write(CONFIG_AD9154_DAC_CS);